Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A carriers synchronizing method of a hybrid frequency parallel inverter is proposed. A low-frequency ripple simulating step is performed to drive a high-frequency controlling unit to simulate a low-frequency ripple. An equidistant grid sampling step is performed to drive the high-frequency controlling unit to sample a sample ripple to generate a sample group and sample the low-frequency ripple to generate a plurality of low-frequency reference groups. An actual shifting angle searching step is performed to drive the high-frequency controlling unit to compare the sample group with the low-frequency reference groups to search an actual shifting angle from the reference shifting angles. A high-frequency carrier adjusting step is performed to drive a proportional integral controller to calculate the actual shifting angle to generate a sync reference, and then a period counter adjusts a starting point of the high-frequency carrier according to the sync reference.

Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A display system and a control method are provided. The display system includes a display device, an illumination device and a control circuit. The display device includes a display panel. The display panel is configured to display an image frame. The illumination device is movably disposed on the display device. The illumination device selectively projects light in a first direction or in a second direction different from the first direction. When the illumination device projects the light in the first direction, the control circuit generates a first control signal so as to control the illumination device to perform a first illumination mode. When the illumination device projects the light in the second direction, the control circuit generates a second control signal so as to control the illumination device to perform a second illumination mode different from the first illumination mode.

Abstract: A display device includes a pixel array substrate and a circuit board. The pixel array substrate has a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. Multiple bonding pads are located on the first surface. The circuit board is bent from above the first surface of the pixel array substrate to below the second surface. The circuit board is electrically connected to the bonding pads and includes a thermoplastic substrate. The thermoplastic substrate includes a third surface facing the pixel array substrate and a fourth surface opposite to the third surface. The thermoplastic substrate includes a first bend formed by thermoplastics.

Abstract: A ballbar testing tune-up method for machine tool includes the steps of letting a machine tool system execute a ballbar test; obtaining a phase characteristic and a peak-value characteristic; creating a Lagrange interpolation polynomial and inputting a servo controller parameter, a phase characteristic and a peak-value characteristic of the machine tool system each time when executing the ballbar test, and obtaining a proposed servo parameter. This method is simple and easy without incurring additional equipment costs, but just using existing equipment to find the proposed servo parameter quickly and input it into a machine tool system, so as to improve the response issue of a servo system and reduce manufacturing contour error to enhance the working precision of the machine tool system.

Abstract: A touch display panel, including a pixel circuit substrate, a color filter substrate, and a display medium layer, is provided. The pixel circuit substrate includes pixel structures, data lines, touch sensing electrodes, touch signal lines, and at least one test circuit. Each pixel structure has an active element and a pixel electrode. The data lines are electrically connected to active elements. The touch sensing electrodes are overlapped with pixel electrodes. The touch signal lines are electrically connected to the touch sensing electrodes. The test circuit is electrically connected to at least part of the touch signal lines or the data lines and includes a peripheral line and first and second test pads. The first and second test pads are respectively disposed on a first side and a second side of a display area. The display medium layer is disposed between the pixel circuit substrate and the color filter substrate.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: An automatic nut screwing device includes a positioning mold plate, a screw shaft, driving gear elements having driving gears, and transmission screwing elements having transmission screw gear units, bolt heads and bolt bodies. The transmission screw gear unit engages an upper out surface of the bolt head. The bolt head of each transmission screw element is fixed with the positioning mold plate. The shaft engaging portion engages with the transmission screw gear unit. The transmission screw gear unit engages with the driving gears such that the transmission screw gear unit is driven to rotate by the shaft engaging portion. A nut socket placing element has nut sockets when the screw shaft is axially rotated to enable the shaft engaging portion of the screw shaft to drive the transmission screw elements, thereby successively rotating elements that result in screw body being rotated to screw with the nut.

Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: An optical film is disclosed. The optical film is divided into a main body and two extending portions arranged along a second direction by two imaginary lines which are extended along a first direction and parallel to each other, wherein the second direction is substantially perpendicular to the first direction. The main body is located between the two extending portions. Each of the extending portions has an abutting edge. A first length W0 of the main body along the first direction is greater than a second length W1 of the abutting edge along the first direction.

Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.

Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.

Abstract: An oral scanner including a heating element, a reflecting element and a temperature difference generating element is provided. The temperature difference generating element has a high temperature end and a low temperature end. The high temperature end is connected to the reflecting element to heat the reflecting element, and the low temperature end is connected to the heating element to cool the heating element.

Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.