Patents by Inventor Fu Chang
Fu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147688Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical bit line, and a first gate surrounding the first semiconductor layer. The memory cell structure also includes a second semiconductor layer surrounding a second portion of the vertical bit line, and a gate dielectric layer surrounding a third portion of the vertical bit line. The gate dielectric layer separates the first semiconductor layer and the first gate from the second semiconductor layer.Type: ApplicationFiled: November 1, 2023Publication date: May 2, 2024Inventor: Fu-Chang Hsu
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Publication number: 20240143322Abstract: A software developer proxy tool accesses microservice applications for a software development project by connecting the developer proxy tool to a common port on a computer network. The tool implements software and hardware to register a plurality of the microservice applications on connection ports that connect to the developer proxy tool at an address for the common port. Data requests among the microservices are handled by the developer proxy tool via the common port. The tool sequentially queries selected microservice applications on the respective connection ports to determine availability for completing a request. The tool receives responses back from microservices and directs the responses back to the requesting program. Failed requests trigger use of remote or third party microservice applications that may be available over an internet connection.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Henry Spivey, Chun-Fu Chang, Wei-Yuan Lo
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Publication number: 20240145448Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Heh-Chang HUANG, Fu-Jen LI, Pei-Haw TSAO, Shyue-Ter LEU
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Publication number: 20240144862Abstract: An electronic device with a first region and a second region located around the first region is disclosed. The electronic device includes a first gate driver and a second gate driver disposed in the second region, and a first transistor and a second transistor disposed in the first region. The first gate driver is used for outputting a first signal. The second gate driver is used for outputting a second signal. The first transistor is used for receiving the first signal from the first gate driver. The second transistor is used for receiving the second signal from the second gate driver. In a top view of the electronic device, the first region has a first side and a second side opposite to the first side, and the first gate driver and the second gate driver are located more adjacent to the first side and away from the second side.Type: ApplicationFiled: January 3, 2024Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Chun-Hsien LIN, Jui-Feng KO, Geng-Fu CHANG
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Publication number: 20240139944Abstract: The robotic arm operating system includes a control device, a plurality of joint devices and a brake release monitoring device. The control device is used to generate an operation instruction. The joint device is coupled to the control device. Each joint device includes a motor and a driver. The drivers of the joint devices receive the operation instruction to generate corresponding multiple unlocking signals. The unlocking signals are used to release a braking state of the motors of the corresponding joint devices. The brake release monitoring device is coupled to the control device and the joint devices, and includes a plurality of monitoring circuits. When one of the plurality of monitoring circuits does not receive the corresponding unlocking signal, the brake release monitoring device notifies the control device that the operation instruction is not allowed.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Inventors: Hsin-Fu WANG, Shun-Kai CHANG, Yen-Shun HUANG
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Publication number: 20240140765Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.Type: ApplicationFiled: September 27, 2023Publication date: May 2, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Caung-Yu Liu
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Patent number: 11973302Abstract: The present disclosure provides a method for aligning a master oscillator power amplifier (MOPA) system. The method includes ramping up a pumping power input into a laser amplifier chain of the MOPA system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the MOPA system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the MOPA system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the MOPA system reaches a steady operational thermal state.Type: GrantFiled: February 20, 2023Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Lin Louis Chang, Henry Tong Yee Shian, Alan Tu, Han-Lung Chang, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
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Patent number: 11972811Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.Type: GrantFiled: August 26, 2021Date of Patent: April 30, 2024Assignee: NEO Semiconductor, Inc.Inventor: Fu-Chang Hsu
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Publication number: 20240135992Abstract: Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.Type: ApplicationFiled: October 17, 2023Publication date: April 25, 2024Inventor: Fu-Chang Hsu
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Publication number: 20240136864Abstract: A wireless power transmission device includes a transmission device and a control device. The control device generates a driving signal to the transmission device in a first soft-start period, so as to drive the transmission device. The control device measures an energy message generated by the transmission device to generate a measurement result in a measurement period, and calculates a signal parameter according to the measurement result. The control device accordingly generates a carrier signal according to the signal parameter obtained by the measurement period in a second soft-start period. In a transmission period, the carrier signal is transmitted to the wireless power-receiving device through the transmission device. The energy message is generated by the transmission device in response to a distance between the transmission device and the wireless power-receiving device.Type: ApplicationFiled: January 6, 2023Publication date: April 25, 2024Inventors: Fu-Chi LIN, Po-Chang CHEN, Wen-Ti LO
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Publication number: 20240135993Abstract: Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.Type: ApplicationFiled: October 22, 2023Publication date: April 25, 2024Inventor: Fu-Chang Hsu
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Publication number: 20240136463Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: EPISTAR CORPORATIONInventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
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Publication number: 20240138154Abstract: Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.Type: ApplicationFiled: October 17, 2023Publication date: April 25, 2024Inventor: Fu-Chang Hsu
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Publication number: 20240126388Abstract: A touch panel sequentially comprising: a first electrode layer, an elastic dielectric layer, and a second structure, the first electrode layer comprises one or more first electrodes in parallel to a first axis, the second structure comprises multiple second circuits in parallel to a second axis, multiple third circuits in parallel to the first axis, multiple second electrodes, and multiple switch circuits, wherein each of the switch circuits connects one of the second electrodes and one of the second circuits, respectively, wherein each of the switch circuits is configured to connect or disconnect the one of the second electrodes and the one of the second circuits according to signals transmitted from one of the third circuits, wherein each of the first electrodes covers at least one of the third circuits, the switch circuits configured by the at least covered one of the third circuits, and the second electrodes corresponding to the switch circuits.Type: ApplicationFiled: August 2, 2023Publication date: April 18, 2024Inventor: Chin-Fu Chang
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Publication number: 20240128291Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.Type: ApplicationFiled: June 6, 2023Publication date: April 18, 2024Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEI-LI WANG, WEN-FU YU, BAE-YINN HWANG
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Publication number: 20240128876Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.Type: ApplicationFiled: June 15, 2023Publication date: April 18, 2024Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
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Publication number: 20240130249Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.Type: ApplicationFiled: August 4, 2023Publication date: April 18, 2024Inventors: Fu-Chang HSU, Kevin HSU
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Publication number: 20240128233Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.Type: ApplicationFiled: June 6, 2023Publication date: April 18, 2024Inventors: CHIA-SHUAI CHANG, WEN-FU YU, BAE-YINN HWANG, WEI-LI WANG, CHIEN-HUNG LIN
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Patent number: RE49942Abstract: In one aspect the present disclosure provides a latching connector. The latching connector comprises a housing that is configured to engage with a mating connector along a coupling axis. The housing includes a lever connected to the housing. The lever is configured to selectively disengage the latching connector from the mating connector. The housing further includes an extending member connected to the lever.Type: GrantFiled: May 8, 2018Date of Patent: April 23, 2024Assignee: Senko Advanced Components, Inc.Inventors: Jeffrey Gniadek, Jimmy Jun-Fu Chang
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Patent number: D1025037Type: GrantFiled: November 12, 2021Date of Patent: April 30, 2024Assignee: WISTRON NEWEB CORPORATIONInventors: Hsiao-Fang Liu, Yu-Fu Kuo, Sun-Hua Chang