Abstract: An antifuse-type non-volatile memory and a control method for the antifuse-type non-volatile memory are provided. During a program action of a program cycle, a timing controller generates a timing control signal. According to the timing control signal, a word line driver is controlled to provide an on voltage and an off voltage to an activated word line. In a total time period of plural on periods, the program current is sufficient to rupture a gate oxide layer of an antifuse transistor in the selected memory cell, and a heating process is completed. Consequently, the gate oxide layer of the antifuse transistor is in a solid rupture state. Consequently, the program action can be successfully performed on the selected memory cell.

Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: A software developer proxy tool accesses microservice applications for a software development project by connecting the developer proxy tool to a common port on a computer network. The tool implements software and hardware to register a plurality of the microservice applications on connection ports that connect to the developer proxy tool at an address for the common port. Data requests among the microservices are handled by the developer proxy tool via the common port. The tool sequentially queries selected microservice applications on the respective connection ports to determine availability for completing a request. The tool receives responses back from microservices and directs the responses back to the requesting program. Failed requests trigger use of remote or third party microservice applications that may be available over an internet connection.

Abstract: An electronic device with a first region and a second region located around the first region is disclosed. The electronic device includes a first gate driver and a second gate driver disposed in the second region, and a first transistor and a second transistor disposed in the first region. The first gate driver is used for outputting a first signal. The second gate driver is used for outputting a second signal. The first transistor is used for receiving the first signal from the first gate driver. The second transistor is used for receiving the second signal from the second gate driver. In a top view of the electronic device, the first region has a first side and a second side opposite to the first side, and the first gate driver and the second gate driver are located more adjacent to the first side and away from the second side.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical bit line, and a first gate surrounding the first semiconductor layer. The memory cell structure also includes a second semiconductor layer surrounding a second portion of the vertical bit line, and a gate dielectric layer surrounding a third portion of the vertical bit line. The gate dielectric layer separates the first semiconductor layer and the first gate from the second semiconductor layer.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.

Abstract: Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.

Abstract: Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.

Abstract: Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

Abstract: A touch panel sequentially comprising: a first electrode layer, an elastic dielectric layer, and a second structure, the first electrode layer comprises one or more first electrodes in parallel to a first axis, the second structure comprises multiple second circuits in parallel to a second axis, multiple third circuits in parallel to the first axis, multiple second electrodes, and multiple switch circuits, wherein each of the switch circuits connects one of the second electrodes and one of the second circuits, respectively, wherein each of the switch circuits is configured to connect or disconnect the one of the second electrodes and the one of the second circuits according to signals transmitted from one of the third circuits, wherein each of the first electrodes covers at least one of the third circuits, the switch circuits configured by the at least covered one of the third circuits, and the second electrodes corresponding to the switch circuits.

Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Abstract: A board, including a first pad area, a second pad area, a first micro heater, a second micro heater, a first heater terminal pad, a second heater terminal pad, and a third heater terminal pad, is provided. The first pad area and the second pad area respectively include at least one pad. The first micro heater and the second micro heater are respectively disposed corresponding to the first pad area and the second pad area. The first heater terminal pad and the second heater terminal pad form a loop with the first micro heater by being electrically connected to an outside, so that the first micro heater generates heat. The second heater terminal pad and the third heater terminal pad form another loop with the second micro heater by being electrically connected to the outside, so that the second micro heater generates heat. A circuit board and a fixture are also provided.

Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

Abstract: A hinge device includes a pivot seat, a rotating shaft, a first friction block, and a locking assembly. By being structurally provided with a sleeve, a first cam ring, a first elastic ring, a second friction block, a second cam ring, a second elastic ring, an elastic element, a locking portion, and a cover of the locking assembly, the hinge device has a locking function and a long service life.

Abstract: A touch function setting method is provided. The method comprising: receiving a sequence parameter which includes multiple clicks, each of the clicks is corresponding to one of areas of a touch panel or screen; receiving a function parameter corresponding to the sequence parameter, the function parameter is corresponding to activate a function; and storing a group of touch function parameters, which includes the sequence parameter and the function parameter.

Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.

Abstract: In one aspect the present disclosure provides a latching connector. The latching connector comprises a housing that is configured to engage with a mating connector along a coupling axis. The housing includes a lever connected to the housing. The lever is configured to selectively disengage the latching connector from the mating connector. The housing further includes an extending member connected to the lever.