Abstract: Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

Abstract: Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.

Abstract: Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.

Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

Abstract: A touch panel sequentially comprising: a first electrode layer, an elastic dielectric layer, and a second structure, the first electrode layer comprises one or more first electrodes in parallel to a first axis, the second structure comprises multiple second circuits in parallel to a second axis, multiple third circuits in parallel to the first axis, multiple second electrodes, and multiple switch circuits, wherein each of the switch circuits connects one of the second electrodes and one of the second circuits, respectively, wherein each of the switch circuits is configured to connect or disconnect the one of the second electrodes and the one of the second circuits according to signals transmitted from one of the third circuits, wherein each of the first electrodes covers at least one of the third circuits, the switch circuits configured by the at least covered one of the third circuits, and the second electrodes corresponding to the switch circuits.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Abstract: A board, including a first pad area, a second pad area, a first micro heater, a second micro heater, a first heater terminal pad, a second heater terminal pad, and a third heater terminal pad, is provided. The first pad area and the second pad area respectively include at least one pad. The first micro heater and the second micro heater are respectively disposed corresponding to the first pad area and the second pad area. The first heater terminal pad and the second heater terminal pad form a loop with the first micro heater by being electrically connected to an outside, so that the first micro heater generates heat. The second heater terminal pad and the third heater terminal pad form another loop with the second micro heater by being electrically connected to the outside, so that the second micro heater generates heat. A circuit board and a fixture are also provided.

Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

Abstract: A hinge device includes a pivot seat, a rotating shaft, a first friction block, and a locking assembly. By being structurally provided with a sleeve, a first cam ring, a first elastic ring, a second friction block, a second cam ring, a second elastic ring, an elastic element, a locking portion, and a cover of the locking assembly, the hinge device has a locking function and a long service life.

Abstract: A touch function setting method is provided. The method comprising: receiving a sequence parameter which includes multiple clicks, each of the clicks is corresponding to one of areas of a touch panel or screen; receiving a function parameter corresponding to the sequence parameter, the function parameter is corresponding to activate a function; and storing a group of touch function parameters, which includes the sequence parameter and the function parameter.

Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.

Abstract: A wearable device includes a main body and a band body. The opposite sides of the main body are provided with a tail portion and a hook portion, respectively. An open groove is provided between the hook portion and other parts of the main body. One end of the band body is connected to the tail portion. The band body enters the open groove from an open side of the open groove and is folded back around the hook portion. The other end of the band body is fixed to a part of the band body, so that the band body is coupled to the hook portion, and the band body is adapted to fix the main body to a subject.

Abstract: An electronic device including a panel, a Chip on Film and a flexible circuit board is disclosed. The panel includes a first gate driver, a switch transistor and a driving transistor. An output terminal of the switch transistor is coupled to a control terminal of the driving transistor. The first gate driver is used for receiving an AC signal and a DC signal and outputting a control signal to a control terminal of the switch transistor. The Chip on Film is electrically connected to the panel and used for transmitting a data signal to an input terminal of the switch transistor and transmitting the AC signal to the first gate driver. The flexible circuit board is electrically connected to the panel and used for transmitting a power signal to an input terminal of the driving transistor and transmitting the DC signal to the first gate driver.

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

Abstract: A multi-fiber, fiber optic connector is interchangeable between a male connector and a female connector by including a pin retainer having a releasable retention device configured to lock the pins in place within the retainer. The retention device may be opened, for example, with a release tool, to free the retention pins for removal of the pins. A method for switching a connector between a male connector configuration and a female connector configuration may be possible as a result of the releasable retention configuration.

Abstract: A wearable device includes a main body and a coupling member. The main body has a tail portion and a hook portion at two opposite sides respectively. One end of the coupling member is connected to the tail portion. A buckle hole of another end of the coupling member is for sleeving onto the hook portion to fix the main body to a subject.

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body having a topmost surface; a first light-emitting device disposed on the carrier body and having a light-emitting surface; and a light-receiving device comprising a group III-V semiconductor material disposed on the carrier body and having a light-receiving surface. The light-emitting surface is separated from the topmost surface by first distant H1, the light-receiving surface is separated from the topmost surface by a second distance H2, and H1 is different from H2.

Abstract: An optical connector has a connector housing assembly for holding one or more ferrules, the connector housing assembly having a height align a vertical alignment axis and a width perpendicular to the height. The connector housing assembly includes an inner front body and an outer release component, the outer release component being movable in relation to the inner front body between a front position and a back position. The optical fiber connector is configured to mate with a receptacle having an upper receptacle hook such that the upper receptacle hook is received in the upper receptacle hook recess and latches with the upper hook retainer surface when the outer release component is in the front position and such that the upper ramp lifts the upper receptacle hook out of the upper receptacle hook recess when the outer release component moves to the back position.

Abstract: In one aspect the present disclosure provides a latching connector. The latching connector comprises a housing that is configured to engage with a mating connector along a coupling axis. The housing includes a lever connected to the housing. The lever is configured to selectively disengage the latching connector from the mating connector. The housing further includes an extending member connected to the lever.