Abstract: A detection device for an optical detection system comprises an optical fiber catheter, having a feed opening and a dome end; and an optical fiber detector, having one end coupled to the optical detection system through a connection terminal, and another end capable of entering an interior of the optical fiber catheter through the feed opening of the optical fiber catheter and reaching the dome end, configured to guide detection light beams generated by the optical detection system to the dome end, and guide reaction light beams corresponding to the detection light beams from the dome end to the optical detection system.

Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.

Abstract: A cylindrical shell detection method includes generating a first and a second terahertz transmitting electromagnetic waves; detecting a plurality of first terahertz reflected electromagnetic waves reflected by the first terahertz transmitting electromagnetic wave incident in a plurality of inner interface layers of a cylindrical shell; detecting a plurality of second terahertz reflected electromagnetic waves reflected by the second terahertz transmitting electromagnetic wave incident in a plurality of outer interface layers of a cylindrical shell; measuring a plurality of first characteristic signals according to the first terahertz transmitting electromagnetic waves and the first terahertz reflected electromagnetic waves to determine a plurality of first characteristics of the plurality of inner interface layers; and measuring a plurality of second characteristic signals according to the second terahertz transmitting electromagnetic waves and the plurality of second terahertz reflected electromagnetic waves

Abstract: A flexible printed circuit board with embedded optical waveguide structure, including a photoelectric transmission unit, wherein the photoelectric transmission unit includes a flexible insulation layer, a first optoelectronic unit and a second optoelectronic unit embedded in the photoelectric transmission unit, at least one redistribution layer having at least one conductive structure stacked with the flexible insulation layer and electrically connected with the first optoelectronic unit and second optoelectronic unit, an optical waveguide structure stacked with the flexible insulation layer, a first metal bump and a second metal bump adjacent to the optical waveguide structure and in optical alignment respectively with the first optoelectronic unit and the second optoelectronic unit to provide reflection planes for optical signal, wherein first metal bump and second metal bump are solid structures made of the same material as the one of redistribution layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: A method for searching a path by using a 3D reconstructed map includes: receiving 3D point-cloud map information and 3D material map information; clustering the 3D point-cloud map information with a clustering algorithm to obtain clustering information, and identifying material attributes of objects in the 3D point-cloud map information with a material neural network model to obtain material attribute information; fusing the those map information based on their coordinate information, thereby outputting fused map information; identifying obstacle areas and non-obstacle areas in the fused map information based on an obstacle neural network model, the clustering information, and the material attribute information; and generating 3D path information according to the non-obstacle areas. Since the 3D path information is generated based on those map information, the obstacle areas and flight spaces are effectively determined to generate an accurate flight path.

Abstract: A semiconductor device that includes an n-buried layer, a p-well region over the n-buried layer, an n-channel MOSFET that includes an n-drain region, and a vertical NPN BJT having a collector that is the n-drain region and a base that is the p-well region. The p-well region is floating.

Abstract: Providing a resistor between a gate of a target device (e.g., a gallium nitride (GaN) high-electron-mobility transistor device) and a clamp circuit improves electrostatic discharge (ESD) protection between an input/output (IO) and the target device. For example, the resistor may result in ESD protection between the IO and a source of the target device and between the IO and a drain of the target device may be at least 2 kilovolts under the human body model. Because ESD protection is improved, chances of burn out in the target device are reduced. Additionally, larger currents may be applied in the clamp circuit without risk of ESD.

Abstract: A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.

Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A 3D printing apparatus including a tank, a print platform, a motor, a force sensor, and a controller is provided. The tank is configured to accommodate a photocurable resin. The print platform is arranged adjacent to the tank. The motor is mechanically connected to the print platform. The motor is configured to drive the print platform to move. The force sensor includes a position encoder. The controller is electrically connected to the force sensor and the motor. The controller is configured to confirm whether the print platform is configured to reach a target position through a value of the position encoder.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A printed circuit board structure includes a plurality of interface layers; and a detection window, arranged in a plurality of detection regions corresponding to a projected position of a detection entrance in the plurality of interface layers, wherein the detection window is utilized for detecting a plurality of characteristics of the plurality of interface layers.

Abstract: Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

Abstract: A touchpad device is provided in the disclosure. The touchpad device includes a touch circuit board, at least two pressure detecting elements, a touch control unit, and a pressure control unit. The touch circuit board includes a touchable zone. The at least two pressure detecting elements are located below the touch circuit board and correspond to at least one pressure sensitive input region in the touchable zone. The touch control unit is electrically connected to the touch circuit board and is configured to receive and process a touch signal from the touch circuit board to generate touch coordinate information. The pressure control unit is electrically connected to the pressure detecting elements and is configured to receive and process a pressure signal detected by the pressure detecting elements in the pressure sensitive input region to generate touch pressure information.

Abstract: A semiconductor ESD protection device includes a pair of source regions, a pair of gate structures, a drain region, a plurality of first conductive contacts, a plurality of second conductive contacts, a plurality of third conductive contacts, and a dummy structure. The pair of gate structures are disposed between the pair of source regions and extend along a direction. The drain region is disposed between the pair of gate structures. Each of the first conductive contacts is disposed on one of the pair of source regions and is arranged along the direction. Each of the plurality of second conductive contacts is disposed on one of the pair of gate structures. The plurality of third conductive contacts are disposed on the drain region and arranged along the direction. The dummy structure is disposed over the drain region and between the gate structures and between the third conductive contacts.