Patents by Inventor Fu-Lung Hsueh

Fu-Lung Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200358398
    Abstract: A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Patent number: 10785865
    Abstract: A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20200287528
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20200274535
    Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10756672
    Abstract: A varainductor includes a signal line, a ground plane, and a floating plane over a substrate. The ground plane is disposed on a side of the signal line, and the first floating plane is disposed between the ground plane and the signal line. An array of switches includes at least two switches configured to selectively electrically connect the ground plane to the floating plane.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMINCONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 10686434
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10672969
    Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Shang-Ying Tsai, Fu-Lung Hsueh, Shih-Ming Yang, Jheng-Yuan Wang, Ming-De Chen
  • Patent number: 10673437
    Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20200153073
    Abstract: A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material surrounds the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material is separated from the first transmission line and the second transmission line.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Jiun Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
  • Publication number: 20200083318
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Patent number: 10530030
    Abstract: A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line. The semiconductor device further includes a dielectric material directly contacting at least one of the first transmission line or the second transmission line, wherein the dielectric material has a different dielectric constant from the high-k dielectric material.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 10510827
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Patent number: 10289777
    Abstract: A method comprises constructing thermal block representations of one or more circuit components or one or more sub-components of the one or more circuit components in an integrated circuit based, at least in part, on defined component parameters. The component parameters describe the one or more sub-components of the one or more circuit components. The thermal block representations have at least one simulation node. The method also comprises supplying a current using at least one current source or voltage controlled current source in a performance simulation. The current is supplied to a thermal path between a first simulation node and a second simulation node. The method further comprises determining a temperature distribution between the first simulation node and the second simulation node based on the current, a first determined voltage at the first simulation node, and a second determined voltage at the second simulation node.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sa-Lly Liu, Szu-Lin Liu, Jaw-Juinn Horng, Fu-Lung Hsueh
  • Publication number: 20190140645
    Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20190097615
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10187046
    Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10177764
    Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20190006571
    Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Ming-Hsien TSAI, Shang-Ying TSAI, Fu-Lung HSUEH, Shih-Ming YANG, Jheng-Yuan WANG, Ming-De CHEN
  • Patent number: 10165208
    Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Calvin Yi-Ping Chao, Fu-Lung Hsueh, Honyih Tu, Jhy-Jyi Sze
  • Publication number: 20180350898
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Application
    Filed: August 10, 2018
    Publication date: December 6, 2018
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann