Patents by Inventor Fu-Lung Hsueh
Fu-Lung Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230354503Abstract: An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.Type: ApplicationFiled: June 29, 2023Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun-Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
-
Publication number: 20230307813Abstract: A method of making a semiconductor device includes forming a first transmission line over a substrate. The method includes forming a second transmission line over the substrate. The method further includes depositing a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The method further includes depositing a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts the first transmission line or the second transmission line.Type: ApplicationFiled: May 4, 2023Publication date: September 28, 2023Inventors: Jiun Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
-
Patent number: 11765975Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.Type: GrantFiled: January 7, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsien Tsai, Shang-Ying Tsai, Fu-Lung Hsueh, Shih-Ming Yang, Jheng-Yuan Wang, Ming-De Chen
-
Patent number: 11737205Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.Type: GrantFiled: August 9, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
-
Patent number: 11711056Abstract: A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.Type: GrantFiled: May 23, 2022Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
-
Patent number: 11664566Abstract: A semiconductor device includes a first transmission line. The semiconductor device includes a second transmission line. The semiconductor device includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts each of the first transmission line and the second transmission line.Type: GrantFiled: January 28, 2022Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
-
Publication number: 20220386451Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun-Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
-
Patent number: 11457525Abstract: An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.Type: GrantFiled: September 18, 2020Date of Patent: September 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
-
Publication number: 20220286087Abstract: A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
-
Publication number: 20220209093Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.Type: ApplicationFiled: January 7, 2022Publication date: June 30, 2022Inventors: Ming-Hsien TSAI, Shang-Ying TSAI, Fu-Lung HSUEH, Shih-Ming YANG, Jheng-Yuan WANG, Ming-De CHEN
-
Patent number: 11362624Abstract: A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.Type: GrantFiled: July 30, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
-
Publication number: 20220158319Abstract: A semiconductor device includes a first transmission line. The semiconductor device includes a second transmission line. The semiconductor device includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts each of the first transmission line and the second transmission line.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: Jiun Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
-
Patent number: 11258151Abstract: A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material surrounds the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material is separated from the first transmission line and the second transmission line.Type: GrantFiled: January 6, 2020Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
-
Patent number: 11251354Abstract: A semiconductor device and method of making same are disclosed. In some embodiments, a method includes: forming a first thermoelectric conduction leg on a substrate; forming a second thermoelectric conduction leg on the substrate to be aligned with the first thermoelectric conduction leg along a same row; forming at least one intermediate thermoelectric conduction structure on an end of the second thermoelectric conduction leg; forming a contact structure to couple the first and second thermoelectric conduction legs via the at least one intermediate thermoelectric conduction structure; and recessing the substrate to form at least one trench substantially adjacent to a respective side edge of either the first thermoelectric conduction leg or the second thermoelectric conduction leg.Type: GrantFiled: June 1, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsien Tsai, Shang-Ying Tsai, Fu-Lung Hsueh, Shih-Ming Yang, Jheng-Yuan Wang, Ming-De Chen
-
Patent number: 11128285Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.Type: GrantFiled: May 26, 2020Date of Patent: September 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
-
Publication number: 20210007215Abstract: An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun-Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
-
Publication number: 20200388741Abstract: A semiconductor device and method of making same are disclosed. In some embodiments, a method includes: forming a first thermoelectric conduction leg on a substrate; forming a second thermoelectric conduction leg on the substrate to be aligned with the first thermoelectric conduction leg along a same row; forming at least one intermediate thermoelectric conduction structure on an end of the second thermoelectric conduction leg; forming a contact structure to couple the first and second thermoelectric conduction legs via the at least one intermediate thermoelectric conduction structure; and recessing the substrate to form at least one trench substantially adjacent to a respective side edge of either the first thermoelectric conduction leg or the second thermoelectric conduction leg.Type: ApplicationFiled: June 1, 2020Publication date: December 10, 2020Inventors: Ming-Hsien TSAI, Shang-Ying TSAI, Fu-Lung HSUEH, Shih-Ming YANG, Jheng-Yuan WANG, Ming-De CHEN
-
Patent number: 10855280Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.Type: GrantFiled: May 14, 2020Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
-
Patent number: 10854708Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.Type: GrantFiled: November 13, 2019Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
-
Publication number: 20200358398Abstract: A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH