Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.

Abstract: A digital code recovery circuit includes a data transmitter that outputs either input data or a preamble code as transmitter data. A radio frequency interconnect (RFI) transmitter modulates carrier signals based on the transmitter data and transmits the modulated carrier signals over a channel to an RFI receiver that demodulates the carrier signals to obtain recovered transmitter data. A calibration storage device stores preamble data and a calibration circuit receives the recovered transmitter data. If the recovered transmitter data originated from the preamble code, the calibration circuit determines a set of digital calibration adjustments from the recovered transmitter data and the preamble data. If the recovered transmitter data originated from the input data, the calibration circuit applies the set of digital calibration adjustments to the recovered transmitter data to obtain adjusted digital code and outputs the adjusted digital code.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Abstract: A method of forming an integrated circuit. The method includes forming at least one transistor and at least one electrical fuse over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate and a work-function metallic layer over the gate dielectric structure. Forming the at least one transistor further includes forming a conductive layer over the work-function metallic layer and a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure. Forming the at least one transistor further includes forming a diffusion barrier layer between the gate dielectric structure and the work-function layer. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. Forming the at least one electrical fuse includes forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer.

Abstract: A varainductor includes a spiral inductor, a ground ring, and a floating ring. The floating ring is disposed between the ground ring and the spiral inductor and surrounds a ring portion of the spiral inductor. A switching element, controlled by a switch control signal, selectively electrically connects the ground ring to the floating ring. The switching element includes one or more switches. The one or more switches are controlled by one or more signals of the switch control signal to adjust the inductance level of the varainductor.

Abstract: A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node.

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: A transmission line design includes a first transmission line configured to transfer at least one first signal. The transmission line design further includes a second transmission line configured to transfer at least one second signal, wherein the second transmission line is spaced from the first transmission line. The transmission line design further includes a high-k dielectric material between the first transmission line and the second transmission line. The transmission line design further includes a dielectric material surrounding the high-k dielectric material, the first transmission line and the second transmission line, wherein the dielectric material is different from the high-k dielectric material.

Abstract: A layout of a portion of an integrated circuit includes first and second cell structures, each including a first or second dummy gate electrode disposed on a first or second boundary of the corresponding first or second cell structure, a first or second edge gate electrode disposed adjacent to the corresponding first or second dummy gate electrode, and a first or second oxide definition (OD) region having a first or second edge. The second boundary faces the first boundary without abutting the first boundary. The first edge of the first OD region is substantially aligned with the closest edge of the first dummy gate electrode or overlaps the first dummy gate electrode. A distance from the first edge gate electrode to the farthest edge of the first dummy gate electrode is greater than the distance from the first edge gate electrode to the first edge of the first OD region.

Abstract: An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level.

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.

Abstract: A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

Abstract: A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.

Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.

Abstract: A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.

Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.

Abstract: A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor.

Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.