Patents by Inventor Fu-Tang Huang

Fu-Tang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872870
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Publication number: 20200258871
    Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 13, 2020
    Inventors: Han-Hung Chen, Yuan-Hung Hsu, Chang-Fu Lin, Rung-Jeng Lin, Fu-Tang Huang
  • Publication number: 20200212019
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Patent number: 10629572
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Publication number: 20200091059
    Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
  • Patent number: 10522453
    Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: December 31, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
  • Patent number: 10510720
    Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: December 17, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Kuo-Hua Yu, Fu-Tang Huang
  • Publication number: 20190259723
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10361150
    Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chee-Key Chung, Yu-Min Lo, Han-Hung Chen, Chang-Fu Lin, Fu-Tang Huang
  • Patent number: 10325872
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Publication number: 20190164941
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 30, 2019
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Patent number: 10199331
    Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Meng-Tsung Lee, Fu-Tang Huang
  • Patent number: 10192834
    Abstract: A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: January 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fu-Tang Huang, Chun-Chi Ke
  • Publication number: 20180288886
    Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.
    Type: Application
    Filed: January 9, 2018
    Publication date: October 4, 2018
    Inventors: Han-Hung Chen, Yuan-Hung Hsu, Chang-Fu Lin, Rung-Jeng Lin, Fu-Tang Huang
  • Publication number: 20180269142
    Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
    Type: Application
    Filed: May 9, 2017
    Publication date: September 20, 2018
    Inventors: Chee-Key Chung, Yu-Min Lo, Han-Hung Chen, Chang-Fu Lin, Fu-Tang Huang
  • Publication number: 20180158784
    Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 7, 2018
    Inventors: Meng-Tsung Lee, Fu-Tang Huang
  • Publication number: 20180130774
    Abstract: A package stack structure is provided, including a first substrate, a second substrate stacked on the first substrate, and an encapsulant formed between the first substrate and the second substrate. A through hole is formed to penetrate the second substrate and allow the encapsulant to be filled therein, thereby increasing the contact area and hence strengthening the bonding between the encapsulant and the second substrate.
    Type: Application
    Filed: February 16, 2017
    Publication date: May 10, 2018
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Kuo-Hua Yu, Fu-Tang Huang
  • Publication number: 20180061810
    Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.
    Type: Application
    Filed: December 8, 2016
    Publication date: March 1, 2018
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Kuo-Hua Yu, Fu-Tang Huang
  • Publication number: 20180063966
    Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.
    Type: Application
    Filed: May 30, 2017
    Publication date: March 1, 2018
    Inventors: Chih-Hsien Chiu, Chen-Wen Huang, Hsin-Lung Chung, Wen-Jung Tsai, Jia-Huei Hung, Fu-Tang Huang
  • Patent number: 9907186
    Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chen-Wen Huang, Hsin-Lung Chung, Wen-Jung Tsai, Jia-Huei Hung, Fu-Tang Huang