Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.

Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.

Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Abstract: A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.

Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.

Abstract: An electronic device package and manufacturing method are provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have, a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Abstract: A package substrate is provided, which includes: a body having opposite first and second surfaces, each having adjacent first and second regions defined thereon; first and second circuit layers formed on the first and second surfaces of the body, respectively; a first insulating layer formed on the first surface of the body and having a plurality of first openings formed in the first insulating layer and positioned in the first and second regions; and a second insulating layer formed on the second surface of the body and having a plurality of second openings formed in the second insulating layer and positioned in the second region. Further, at least a third opening is formed in the second insulating layer and positioned in the first region to reduce the volume of the second insulating layer, thereby facilitating even distribution of thermal stresses through the first and second insulating layers during thermal cycling and hence preventing warpage of the package substrate.