Abstract: A socket wrench and light source arrangement includes a wrench, and a socket coupled to the wrench which is alternatively set between a front working position and a rear working position. A battery is installed in the wrench. A lamp holder assembly is installed in the socket and adapted to emit light through the front open side of the socket. The lamp holder assembly is electrically connected to the battery to emit light when the socket is set in the rear working position, or electrically disconnected from the battery to turn off light when the socket is set in the front working position or separated from the wrench.

Abstract: A method is disclosed for forming the lower storage node and contact for capacitors on a semiconductor wafer. The method includes an etch back process to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer. When a contact plug is formed during a subsequent deposition process, the rounded shoulder results in local enlargement of the contact plug as well as filleting of reentrant corners. The contact plug therefore sustains substantially reduced mechanical stress during subsequent wafer cleaning processes. This stress reduction results in a reduced rate of lower node collapse and increased production yield of finished product.

Abstract: A method for forming a capacitor in DRAM is disclosed. The method includes: providing a conductor defined on a first dielectric layer; forming a second dielectric layer on the conductor; then forming a polysilicon layer on the second dielectric layer, the polysilicon layer serves as an etching mask; next, etching the second dielectric layer; removing said polysilicon layer; etching said conductor; and finally removing said second dielectric layer.

Abstract: A silicon oxide layer is formed on a substrate surface of a semiconductor wafer. A node contact is formed in the silicon oxide layer. A storage node is formed on the silicon oxide layer and connects to the node contact. An ion implantation process is performed as a surface process on the silicon oxide layer. A silicon nitride layer is subsequently formed on the surfaces of the silicon oxide layer and the storage node. Finally, a high-temperature oxidation process is performed. The surface process reduces the difference in the incubation time for the silicon nitride layer deposited on the silicon oxide layer and on the surface of the storage node. The surface process also relieves problems associated with the nonuniformity in thickness of the silicon nitride layer. Neck-oxidation at the interface of the storage node and the node contact is thus prevented.

Abstract: The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole.

Abstract: A fabrication method for a borderless buried bit line is described. A substrate wherein a plurality of word lines and source/drain regions formed thereon is provided. A first insulation material is formed over the substrate and a node landing pad is formed in the first insulation material, wherein the node landing pad is covered by a second insulation material. A bit line contact is further formed in the first insulation material, wherein the bit line contact is covered by a third insulation material. Therefore, a trench is further formed along the sides of the bit line contact, traversing across the first insulation material. A partial filling of the trench with a conductive material, followed by filling the trench with a fourth insulation layer to complete the formation of the buried bit line.

Abstract: A method for forming a MOSFET is described. The feature of this invention is that an epitaxial silicon layer with device isolation structures is formed over a substrate, wherein each device isolation structure is made of oxide. The invention need not etch the substrate for forming a device isolation structure. As a result, the invention not only prevents stress and dislocation generation and avoids leakage current, but also provides an easily method for forming a device isolation structure.

Abstract: A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole.

Abstract: A method of forming a borderless contact is described. An ion implantation process and a thermal process are performed on a device isolation structure to form a silicon nitride layer therein. During a process of forming a borderless contact window, the silicon nitride layer can serve as an etching stop layer to protect the device isolation structure from overetching. As a result, no recess is formed, and leakage current is avoided.

Abstract: A method of fabricating a node contact hole is disclosed. The fabrication includes the steps as follows. At first, the first interpoly dielectric (IPD1) layer is formed over the semiconductor substrate. The landing pad is formed in the first interpoly dielectric layer. The polycide bit line is formed on the first interpoly dielectric layer. Afterwards, the second interpoly dielectric (IPD2) layer is formed over the first interpoly dielectric layer. Next, the defined photoresist layer is formed on the second interpoly dielectric layer, then using reflow and curing processes to form the heated photoresist layer. Afterwards, a portion of the second interpoly dielectric layer is firstly etched, using the heated photoresist layer as a mask. The depth is formed in the second interpoly dielectric layer. Then the heated photoresist layer is removed. Next, in order to the silicon nitride layer and the polysilicon layer are deposited over the second interpoly dielectric layer.

Abstract: A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H3PO4) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H3PO4 wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.

Abstract: A method of fabricating a bottom electrode for a capacitor is described in which a dielectric layer is formed on a substrate already comprising an isolation layer, an etching stop layer and a landing pad. Bit line structures and spacers are further formed on the dielectric layer. A node contact window opening is formed in the dielectric layer, exposing the landing pad, and a conformal first conductive layer is formed on the substrate. After a specially patterned mask layer is formed and the exposed first conductive layer is removed, an extended portion is formed connecting to the conductive layer to complete the fabrication of the columnar bottom electrode for a capacitor.

Abstract: A method of fabricating a narrow bit line structure is disclosed. The fabrication includes the steps as follows. At first, the interpoly dielectric layer is formed over the MOSFET. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer, the tungsten silicide layer, the silicon-oxy-nitride layer, and the second polysilicon layer is continuously formed over the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall. The silicon oxide layer is deposited over the second polysilicon layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer.

Abstract: A method of fabricating a capacitor on a substrate. The method includes sequentially forming a first dielectric layer and an etching barrier layer on the substrate, the etching barrier layer and the first dielectric layer having an opening formed therein. A conductive layer is formed on the etching barrier layer and fills the opening. The conductive layer is patterned to form a raised region on the conductive layer. Isolation spacers and conductive spacers are alternately formed on sidewalls of the raised region. The isolation spacers and the conductive spacers are concentrically layered. The isolation spacers are used as masks to remove the conductive spacers and a portion of the patterned conductive layer. The etching barrier layer is used as an etch stop layer. The isolation spacers and a portion of the patterned conductive layer are removed. The remaining patterned conductive layer forms a storage electrode of the capacitor.

Abstract: A method of forming a dual cylindrical capacitor on a semiconductor substrate having at least a device isolation structure and a transistor thereon is provided, wherein the transistor includes at least a gate and a source/drain region. A first insulation layer and a second insulation layer are formed on the substrate. An opening comprising an lower part penetrating through the first insulation layer and an upper part penetrating through the second insulation layer is formed to expose the source/drain region. A conductive layer is formed on the second insulation layer to fill the lower part of the opening and to cover a surface of the upper part of the opening. A spacer is formed on a part of the conductive layer on a side wall of the larger opening. A conductive spacer is formed on the spacer. The spacer is removed.

Abstract: A method is provided for fabricating a data-storage capacitor for a DRAM device, which can help increase the capacitance of the resulted capacitor. By this method, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially formed over the substrate. An opening is formed in the third insulating layer, and a contact hole is formed to expose a source/drain region in the substrate. Subsequently, a conductive layer is formed over the third insulating layer, which is electrically connected to the exposed source/drain region. Next, a fourth insulating layer is formed over the conductive layer. A surface part of the third and fourth insulating layers is removed until reaching a predefined depth to allow an upper part of the conductive layer to be exposed. Next, conductive sidewall spacers are formed on the exposed part of the conductive layer to increase the surface area of the conductive layer.

Abstract: A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

Abstract: The infusion of TIL586 along with interleukin-2 (IL-2) into the autologous patient with metastatic melanoma resulted in the objective regression of tumor. A gene encoding a tumor antigen recognized by TIL586 was previously isolated and shown to encode gp75 or TRP-1. The present invention relates to the identification of a second tumor antigen recognized by a HLA-A31 restricted CTL clone derived from the TIL586 cell line. This antigen derived from the TRP-2 protein tumor antigen and peptides thereof are capable of sensitizing target cells for lysis by a CTL clone at 1 nM peptide concentration. Modified peptides were also recognized by the CTL clone.