Patents by Inventor Fu Wu
Fu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220343958Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.Type: ApplicationFiled: July 7, 2022Publication date: October 27, 2022Inventors: Chih-Chieh CHIU, Chia-En HUANG, Fu-An WU, I-Han HUANG, Jung-Ping YANG
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Patent number: 11468929Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: GrantFiled: April 20, 2021Date of Patent: October 11, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
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Publication number: 20220308283Abstract: An optical film is disclosed. The optical film is divided into a main body and two extending portions arranged along a second direction by two imaginary lines which are extended along a first direction and parallel to each other, wherein the second direction is substantially perpendicular to the first direction. The main body is located between the two extending portions. Each of the extending portions has an abutting edge. A first length W0 of the main body along the first direction is greater than a second length W1 of the abutting edge along the first direction.Type: ApplicationFiled: April 7, 2022Publication date: September 29, 2022Inventors: Yi-Jen CHIU, Sung-Fu WU, Ying-Ting CHEN
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Publication number: 20220277781Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: ApplicationFiled: April 20, 2021Publication date: September 1, 2022Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
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Publication number: 20220269467Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.Type: ApplicationFiled: January 10, 2022Publication date: August 25, 2022Applicant: QISDA CORPORATIONInventors: Hao-Chun Tung, Hsin-Che Hsieh, Wei-Jou Chen, Po-Fu Wu, Yu-Fu Fan, Chih-Ming Chang
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Patent number: 11417377Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.Type: GrantFiled: September 14, 2020Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
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Publication number: 20220249209Abstract: An oral scanner including a heating element, a reflecting element and a temperature difference generating element is provided. The temperature difference generating element has a high temperature end and a low temperature end. The high temperature end is connected to the reflecting element to heat the reflecting element, and the low temperature end is connected to the heating element to cool the heating element.Type: ApplicationFiled: January 24, 2022Publication date: August 11, 2022Applicant: Qisda CorporationInventors: Chien-Hung LIN, Po-Fu WU, Jun-Ming SHEN, Szu-Fan CHEN, Yi-Ling LO
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Publication number: 20220255538Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: ApplicationFiled: April 29, 2022Publication date: August 11, 2022Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20220252873Abstract: An calibration kit includes a base, a combination of calibration parts, and a manipulation part. The combination of calibration parts is disposed on the base and includes a first calibration part and a second calibration part. The first calibration part has a first calibration surface. The second calibration part has a second calibration surface. The first calibration part and the second calibration part are relatively movable in a movement direction and are movable relative to the base. The manipulation part is movably or rotatably disposed on the base. The manipulation part is configured to be operable to drive the first calibration part and the second calibration part to move in the movement direction relative to the base, so that the combination of calibration parts forms a three-dimensional calibration surface configuration through the first calibration surface and the second calibration surface.Type: ApplicationFiled: September 6, 2021Publication date: August 11, 2022Applicant: QISDA CORPORATIONInventors: Tzu-Huan Hsu, Po-Fu Wu, Yuan-Yu Hsiao, Ching-Huey Wang, Chih-Kang Peng, Chun-Ming Shen, Chih-Ming Hu, Yi-Ling Lo
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Publication number: 20220236894Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
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Patent number: 11362599Abstract: A controlling method is for a single-phase bidirectional inverter. The single-phase bidirectional inverter includes a switch and an inductor. The controlling method for the single-phase bidirectional inverter includes an extracting step, a calculating step, and an integrating step. In the extracting step, a current command is inputted to the switch and obtaining a current through the inductor. The current is piecewisely linearized to extract a magnetizing inductance and a demagnetizing inductance of the inductor. In the calculating step, a duty ratio of the switch is used to calculate a variation of the current of the magnetizing inductance and a variation of the current of the demagnetizing inductance. In the integrating step, the variation of the current of the magnetizing inductance and the variation of the current of the demagnetizing inductance are integrated to obtain another duty ratio of the switch in the next cycle.Type: GrantFiled: June 21, 2020Date of Patent: June 14, 2022Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Tsai-Fu Wu, Temir Sakavov, Yen-Hsiang Huang, Yun-Tsung Liu
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Patent number: 11355656Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the base, and the photosensitive element is configured to receive a light beam traveling along an optical axis.Type: GrantFiled: April 17, 2020Date of Patent: June 7, 2022Assignee: TDK TAIWAN CORP.Inventors: Chen-Er Hsu, Sin-Jhong Song, Chi-Fu Wu, Hao-Yu Wu, Tsutomu Fukai, Ming-Hung Wu
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Publication number: 20220168856Abstract: An automatic nut screwing device includes a positioning mold plate, a screw shaft, driving gear elements having driving gears, and transmission screwing elements having transmission screw gear units, bolt heads and bolt bodies. The transmission screw gear unit engages an upper out surface of the bolt head. The bolt head of each transmission screw element is fixed with the positioning mold plate. The shaft engaging portion engages with the transmission screw gear unit. The transmission screw gear unit engages with the driving gears such that the transmission screw gear unit is driven to rotate by the shaft engaging portion. A nut socket placing element has nut sockets when the screw shaft is axially rotated to enable the shaft engaging portion of the screw shaft to drive the transmission screw elements, thereby successively rotating elements that result in screw body being rotated to screw with the nut.Type: ApplicationFiled: December 21, 2020Publication date: June 2, 2022Applicant: SUMEEKO INDUSTRIES CO., LTD.Inventors: Hsin Wei LEE, Kuang Yu CHEN, Shen Fu WU, Ming Yuan CHEN
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Patent number: 11323101Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: GrantFiled: March 12, 2021Date of Patent: May 3, 2022Assignee: AIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Fu-An Wu, Yangsyu Lin, Chiting Cheng, Cheng Hung Lee, Chen-Lin Yang
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Patent number: 11309443Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the integrated package substrate, and the photosensitive element is configured to receive a light beam traveling along an optical axis.Type: GrantFiled: April 17, 2020Date of Patent: April 19, 2022Assignee: TDK Taiwan Corp.Inventors: Chen-Er Hsu, Sin-Jhong Song, Chi-Fu Wu, Hao-Yu Wu, Tsutomu Fukai, Ming-Hung Wu
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Patent number: 11301148Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.Type: GrantFiled: March 15, 2021Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
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Patent number: 11269020Abstract: A plurality of test pads are formed on a first substrate or a second substrate. A plurality of first solder joints are reserved on a first surface of the first substrate, and each of the first solder joints is coupled to at least a test pad or to another first solder joint through at least a first trace. A plurality of second solder joints are reserved on a second surface of the second substrate. Each of the second solder joints is coupled to at least a test pad or to another second solder joint through at least a second trace. A plurality of dummy solder balls are formed between the first solder joints and the second solder joints. Probes are coupled to the test pads to measure circuit characteristics between the test pads.Type: GrantFiled: December 23, 2019Date of Patent: March 8, 2022Assignee: Qisda CorporationInventor: Po-Fu Wu
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Patent number: 11262965Abstract: The present invention provides a display device. The display device includes a display module, a first mounting frame, one or more electromotive driving elements, and a control module. The display module is disposed on and spaced from a setting surface and has a display surface. The first mounting frame is spaced from the display module and is disposed on the setting surface. The electromotive driving elements are disposed on the first mounting frame and face the display module relatively. The control module controls display of the display surface based on a display signal, and controls each of the electromotive driving elements to selectively generate an attractive force and a repulsive force with respect to the display module based on an actuation signal, so as to change a distance of the display module from the first mounting frame, a setting angle of the display module with respect to the setting surface, or a combination thereof.Type: GrantFiled: January 13, 2021Date of Patent: March 1, 2022Assignee: QISDA CORPORATIONInventor: Po-Fu Wu
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Patent number: 11237382Abstract: An optical module includes a driving unit, a first color wheel, a second color wheel, a first electromagnet, a plurality of first magnets and a polarity control unit. The driving unit has a rotating shaft. The first color wheel is fixed on the rotating shaft. The second color wheel is freely disposed on the rotating shaft. The first electromagnet is disposed on the first color wheel and the first magnets are disposed on the second color wheel. The driving unit drives the first color wheel to rotate, such that the first electromagnet rotates along with the first color wheel. The polarity control unit controls a direction of current flow in the first electromagnet to control a polarity of the first electromagnet, such that the first electromagnet attracts one of the first magnets during rotation to drive the second color wheel to rotate along with the first color wheel.Type: GrantFiled: July 29, 2019Date of Patent: February 1, 2022Assignee: Qisda CorporationInventor: Po-Fu Wu
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Publication number: 20220003405Abstract: A display system and a control method are provided. The display system includes a display device, an illumination device and a control circuit. The display device includes a display panel. The display panel is configured to display an image frame. The illumination device is movably disposed on the display device. The illumination device selectively projects light in a first direction or in a second direction different from the first direction. When the illumination device projects the light in the first direction, the control circuit generates a first control signal so as to control the illumination device to perform a first illumination mode. When the illumination device projects the light in the second direction, the control circuit generates a second control signal so as to control the illumination device to perform a second illumination mode different from the first illumination mode.Type: ApplicationFiled: June 21, 2021Publication date: January 6, 2022Applicant: QISDA CORPORATIONInventors: Hsin-Che Hsieh, Wei-Jou Chen, Yu-Fu Fan, Po-Fu Wu