Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

Abstract: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and die pad supports are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side are ended at a side surface of the plastic package. In order to reduce the length between the semiconductor die and the leads, the lead tips on the one side are extended to positions close to the die pad, and the intervals between adjoining leads on the one side are smaller than those on the other side.

Abstract: This manufacturing method of a semiconductor device prepares a lead frame to which a heat spreader, and the tip parts of a plurality of inner leads were joined via a thermoplastic insulating binding material, arranges a lead frame on a heat stage, and joins the semiconductor chip to the heat spreader via the thermoplastic binding material which was heated and softened after having arranged the semiconductor chip on the heat spreader. Die bonding can be performed without scattering inner leads by joining the semiconductor chip and the thermoplastic binding material, suppressing the tip parts of the inner leads to the heat stage side. Improvement in the assembling property of a semiconductor device can be aimed at.

Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

Abstract: A method for analysis of solvent evaporation patterns includes: continuously evacuating the gas of a single-component or multicomponent solvent evaporated under desired evaporation conditions from an object containing the single-component or multicomponent solvent housed in an airtight container, with evacuation means from the airtight container to an exhaust path connected to an exhaust port of the evacuation means; sampling a gas at predetermined time intervals from a desired point between the airtight container and the outlet of the exhaust path with the continuous evacuation maintained; measuring the solvent gas contained in the sampled gas; and determining an evaporation pattern of the solvent from the object under the desired evaporation conditions, from results of the measurement.

Abstract: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and die pad supports are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side are ended at a side surface of the plastic package. In order to reduce the length between the semiconductor die and the leads, the lead tips on the one side are extended to positions close to the die pad, and the intervals between adjoining leads on the one side are smaller than those on the other side.

Abstract: A semiconductor device is manufactured by adhering a fixing tape to plural leads of a lead frame comprising a copper alloy, mounting a semiconductor chip on a tab of the lead frame, electrically connecting the leads to electrodes a of the semiconductor chip via bonding wires, forming a sealing resin portion that seals the semiconductor chip, the tab, the bonding wires, the leads and the fixing tape, and cutting the lead frame. A binder layer of the fixing tape includes at least % by weight of an amine-curable epoxy resin as its main component, and does not include a phenol resin. The binder layer of the fixing tape further includes no more than % by weight of acrylonitrile butadiene rubber. By using this material for the binder layer of the fixing tape, migration of the copper in the leads is suppressed even when a degradation test with strict environmental degradation conditions is conducted.

Abstract: The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar (21d) irrespective of the inner lead (21b) pitch, by making the pitch of the pad (22a) smaller than the pitch of the inner lead (21b), or by forming the pad (22a) in a zigzag arrangement.

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.

Abstract: Miniaturization in a semiconductor device which has a chip part is attained. A QFP having the chip part includes a semiconductor chip, a plurality of inner leads arranged around the semiconductor chip, a sheet member which connects with the end part of the inner lead via insulating adhesive and which connects with the semiconductor chip via adhesive, a plurality of outer leads which are respectively integral with an inner lead, a plurality of wires which connect the pads of the semiconductor chip and a plurality of inner leads, respectively, and a bar lead arranged along the periphery of a plurality of inner leads in the domain between the semiconductor chip and the plurality of inner leads. In the domain between the semiconductor chip and a plurality of inner leads, the chip part which constitutes a surface mounting part is mounted on the bar lead, while being arranged beneath the wire.

Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: A surface mounting method for mounting semiconductor devices suppresses solder peeling defects which tried to occur during mounting. The method used for mounting semiconductor devices includes a process for preparing the semiconductor devices by obtaining multiple terminals by exposing a section of each of multiple leads protruding from a rear side of the plastic casing, and forming a layer of solder by solidifying a molten solder material; a process for supplying a solder paste material to multiple electrodes on a printed circuit board; and a process for melting the solder paste of the multiple electrodes and connecting each of the multiple terminals with the multiple electrodes.

Abstract: A method for manufacturing a semiconductor device includes the steps of providing a semiconductor device of a surface mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be smaller than the main surface of the semiconductor chip, accommodating the semiconductor device into a non-moistureproof, e.g., flammable, packing, and shipping the packed semiconductor device. The non-moistureproof packing may have a moisture permeability of T T?1 g/m2/24 hr. The method may also include providing a second semiconductor device of a surface-mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be larger than the main surface of the semiconductor chip, moistureproof-packing the second semiconductor device, and shipping and packed second semiconductor device.

Abstract: A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer.