Patents by Inventor Fujio Ito
Fujio Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6893898Abstract: A semiconductor device comprising a semiconductor chip with plural electrodes arranged on a main surface thereof, plural leads electrically connected respectively to the plural electrodes on the semiconductor chip, and a resin sealing body which seals the semiconductor chip and the plural leads, wherein the plural leads include first leads and second leads adjacent to the first leads, the first leads having first external connections exposed from a mounting surface of the resin sealing body and positioned near a side face of the resin sealing body, the second leads having second external connections exposed from the mounting surface of the resin sealing body and positioned closer to the semiconductor chip with respect to the first external connections. The first and second leads are fixed to the semiconductor chip. The semiconductor device is suitable for a multi-pin structure and the manufacturing yield thereof is improved.Type: GrantFiled: May 29, 2003Date of Patent: May 17, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Fujio Ito, Hiromichi Suzuki
-
Publication number: 20040262752Abstract: A semiconductor chip has a plurality of electrodes arranged along one side thereof; a plurality of leads arranged outside the one side thereof in the same direction as the above side; a plurality of bonding wires electrically connecting the electrodes to the leads; and a resin sealing member sealing the semiconductor chip, the leads and the bonding wires. The leads include first leads, each having a terminal portion which is located on the side face of the resin sealing member and exposed from the rear surface thereof, and second leads, each having a terminal portion which is located on the inner side of the terminal portions of the first leads and exposed from the rear surface of the resin sealing member. The first leads and the second leads are arranged alternately. The plurality of bonding wires are connected to the respective leads on the inner side of the terminal portions of the first leads.Type: ApplicationFiled: June 4, 2004Publication date: December 30, 2004Inventors: Fujio Ito, Hiromichi Suzuki, Takafumi Konno, Tsugio Umehara
-
Publication number: 20040232528Abstract: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and die pad supports are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side are ended at a side surface of the plastic package. In order to reduce the length between the semiconductor die and the leads, the lead tips on the one side are extended to positions close to the die pad, and the intervals between adjoining leads on the one side are smaller than those on the other side.Type: ApplicationFiled: June 29, 2004Publication date: November 25, 2004Inventors: Fujio Ito, Hiromicti Suzuki
-
Publication number: 20040232527Abstract: A semiconductor device is disclosed which is improved in the mounting reliability and which has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.Type: ApplicationFiled: May 20, 2004Publication date: November 25, 2004Inventors: Fujio Ito, Hiromichi Suzuki
-
Patent number: 6809405Abstract: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and die pad supports are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side are ended at a side surface of the plastic package. In order to reduce the length between the semiconductor die and the leads, the lead tips on the one side are extended to positions close to the die pad, and the intervals between adjoining leads on the one side are smaller than those on the other side.Type: GrantFiled: November 20, 2002Date of Patent: October 26, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Fujio Ito, Hiromicti Suzuki
-
Patent number: 6803258Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: May 23, 2002Date of Patent: October 12, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
-
Patent number: 6791182Abstract: At least a part of the inner leads 1a of a lead frame 1 is covered with a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating. The metal or alloy is selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of defects, such as leakage and shorting, due to ion migration can be prevented.Type: GrantFiled: March 25, 2002Date of Patent: September 14, 2004Assignee: Renesas Technology Corp.Inventors: Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii, Hiromichi Suzuki, Fujio Ito, Takafumi Nishita, Akihiko Kameoka, Masaru Yamada
-
Patent number: 6780679Abstract: The mounting reliability of a QFN (Quad Flat Non-leaded package) having a large number of pins is improved, and also the manufacturing cost of the QFN having a large number of pins is reduced. A die pad, on which a semiconductor die is mounted, is arranged at the center of a plastic package constituting a package of the QFN. A plurality of leads are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side terminate at a side surface of the plastic package. On a rear surface of the plastic package, external connection terminals formed by pressing and bending the respective parts of the plurality of leads protrude to the outside, and a solder layer is formed on each surface of the terminals.Type: GrantFiled: December 19, 2002Date of Patent: August 24, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Fujio Ito, Hiromichi Suzuki
-
Publication number: 20040159922Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: ApplicationFiled: February 13, 2004Publication date: August 19, 2004Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
-
Patent number: 6767209Abstract: Relates to an interdental cleaning tool provided on the peripheral surface of a shaft member 1 with one or a plurality of projections 2, the projections being pinnulate elements or cirrate elements, and shaft member 1 and projections 2 being integrally molded from synthetic resin, whereby there may be afforded a soft touch against the tissues of the oral cavity during use, deviation in extraction force of the pinnulate members and cirrate members may be prevented, and production costs may be reduced.Type: GrantFiled: August 3, 2001Date of Patent: July 27, 2004Assignees: Sunstar Inc., Uni-Sunstar B.V.Inventors: Yoshikazu Tomita, Fujio Ito, Naoki Tsurukawa, Hitoshi Matsumoto
-
Publication number: 20040124506Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.Type: ApplicationFiled: December 9, 2003Publication date: July 1, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Eastern Japan Semiconductor, Inc.Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
-
Publication number: 20040126932Abstract: A method of manufacturing a semiconductor device is provided including preparing a lead frame having a plurality of leads, wherein the lead widths of the lead tips are smaller than the lead thickness of the tips. A plate is also prepared having a first portion and second portion on a main surface thereof, the second portion being located at the outer periphery of said first portion. A semiconductor chip having a semiconductor element and a plurality of electrodes is fastened to the first portion of the plate and the lead tips are fastened on the second portion of the plate. Bonding wires are then formed to electrically connect the lead tips and the electrodes of the semiconductor chip, and then the lead tips, the plate, the semiconductor chip and the bonding wires are sealed with a molding member.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
-
Patent number: 6692989Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: GrantFiled: February 24, 2003Date of Patent: February 17, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems, Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
-
Patent number: 6673655Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: May 23, 2002Date of Patent: January 6, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
-
Publication number: 20030228720Abstract: A semiconductor device comprising a semiconductor chip with plural electrodes arranged on a main surface thereof, plural leads electrically connected respectively to the plural electrodes on the semiconductor chip, and a resin sealing body which seals the semiconductor chip and the plural leads, wherein the plural leads include first leads and second leads adjacent to the first leads, the first leads having first external connections exposed from a mounting surface of the resin sealing body and positioned near a side face of the resin sealing body, the second leads having second external connections exposed from the mounting surface of the resin sealing body and positioned closer to the semiconductor chip with respect to the first external connections. The first and second leads are fixed to the semiconductor chip. The semiconductor device is suitable for a multi-pin structure and the manufacturing yield thereof is improved.Type: ApplicationFiled: May 29, 2003Publication date: December 11, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Fujio Ito, Hiromichi Suzuki
-
Publication number: 20030209815Abstract: In order to improve the mounting accuracy of QFN (Quad Flat Non-leaded package) having external connection terminals on a rear surface of the package, a semiconductor device and its manufacturing method are provided. In the QFN, notch sections are provided in the two diagonal corner portions on the front surface of the sealing body. Reference marks with a circular form are formed in the parts of the suspension leads exposed from the notch sections so that the positions of the reference marks can be optically detected from above the sealing body when mounting the QFN to the wiring board. The reference marks are formed by the etching to remove the parts of the metal plate that constitutes the suspension leads or by pressing the parts to punch them.Type: ApplicationFiled: May 7, 2003Publication date: November 13, 2003Inventors: Fujio Ito, Hiromichi Suzuki
-
Publication number: 20030178723Abstract: The mounting reliability of a QFN (Quad Flat Non-leaded package) having a large number of pins is improved, and also the manufacturing cost of the QFN having a large number of pins is reduced. A die pad, on which a semiconductor die is mounted, is arranged at the center of a plastic package constituting a package of the QFN. A plurality of leads are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side terminate at a side surface of the plastic package. On a rear surface of the plastic package, external connection terminals formed by pressing and bending the respective parts of the plurality of leads protrude to the outside, and a solder layer is formed on each surface of the terminals.Type: ApplicationFiled: December 19, 2002Publication date: September 25, 2003Inventors: Fujio Ito, Hiromichi Suzuki
-
Publication number: 20030124770Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: ApplicationFiled: February 24, 2003Publication date: July 3, 2003Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
-
Publication number: 20030111717Abstract: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and die pad supports are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side are ended at a side surface of the plastic package. In order to reduce the length between the semiconductor die and the leads, the lead tips on the one side are extended to positions close to the die pad, and the intervals between adjoining leads on the one side are smaller than those on the other side.Type: ApplicationFiled: November 20, 2002Publication date: June 19, 2003Inventors: Fujio Ito, Hiromicti Suzuki
-
Patent number: 6558980Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: GrantFiled: April 11, 2001Date of Patent: May 6, 2003Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi