Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: Apparatus and methods are disclosed, including receiving an indication to selectively overwrite first data stored on a first page of a first subset of a group of multi-level memory cells of a storage system, determining a second subset of memory cells from the first subset that, in response to programming from a first level to a second level, will alter a read output of the first data on the first page and maintain a read output of remaining pages, and programming the second subset of memory cells from the first level to the second level to securely remove the first data stored on the first page while maintaining data on the remaining pages.

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: Apparatus and methods are disclosed, including receiving an indication to selectively overwrite first data stored on a first page of a first subset of a group of multi-level memory cells of a storage system, determining a second subset of memory cells from the first subset that, in response to programming from a first level to a second level, will alter a read output of the first data on the first page and maintain a read output of remaining pages, and programming the second subset of memory cells from the first level to the second level to securely remove the first data stored on the first page while maintaining data on the remaining pages.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: Devices and techniques for accelerated memory device trim initialization are described herein. An initialization of a memory device can be started by the memory device. An accelerated trim command can be received at the memory device from a controller. The memory device can refrain from setting a trim in response to receipt of the accelerated trim command. Here, the trim is expected to be set by the controller. The memory device can then complete the initialization after the trim is set by the controller.

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.

Abstract: A memory device comprises a memory array and a memory control unit. The memory includes multi-level memory cells. The memory control unit is configured to: initiate programming of memory cells of the memory array using a first pass programming operation, wherein the first pass programming operation places programming data using a first and second voltage threshold distributions; read programmed memory cells using a first read voltage level on word lines of the memory cells; read the programmed memory cells using a second read voltage level on the word lines of the memory cells; determine a number of the programmed memory cells with a voltage threshold placed between the first and second voltage threshold distributions by the programming; and suspend second pass programming of the memory cells in response to the determined number of cells exceeding a specified threshold number, and initiate a second pass programming operation otherwise.

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

Abstract: Aspects of the present disclosure include accessing block data stored in a memory component including memory blocks. The block data identifies bad blocks and reusable bad blocks, the reusable bad blocks having a higher level of reliability than bad blocks. Block selection is performed to select a block based on a block address. Based on the block selection and based on the block data, a tag operation is performed by setting a latch of the selected block to a first state in which access to the selected block is disabled.

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.

Abstract: A memory device comprises a memory array and a memory control unit. The memory includes multi-level memory cells. The memory control unit is configured to: initiate programming of memory cells of the memory array using a first pass programming operation, wherein the first pass programming operation places programming data using a first and second voltage threshold distributions; read programmed memory cells using a first read voltage level on word lines of the memory cells; read the programmed memory cells using a second read voltage level on the word lines of the memory cells; determine a number of the programmed memory cells with a voltage threshold placed between the first and second voltage threshold distributions by the programming; and suspend second pass programming of the memory cells in response to the determined number of cells exceeding a specified threshold number, and initiate a second pass programming operation otherwise.

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.