Patents by Inventor Fumiaki Toyama

Fumiaki Toyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11114459
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 7, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takaaki Iwai, Hirofumi Tokita, Yoshitaka Otsu, Fumiaki Toyama, Yuki Mizutani
  • Patent number: 11081443
    Abstract: A first vertically alternating sequence of first insulating layers and first spacer material layers and a first-tier retro-stepped dielectric material portion are formed over a substrate. The first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers. A second vertically alternating sequence of second insulating layers and second spacer material layers and a second-tier retro-stepped dielectric material portion are formed over the first vertically alternating sequence and the first-tier retro-stepped dielectric material portion. The second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers. An opening is formed through the second vertically alternating sequence over the first-tier retro-stepped dielectric material portion, and is filled with a dielectric well structure.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 3, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuki Mizutani, Masayuki Hiroi, Fumiaki Toyama
  • Publication number: 20210233900
    Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Jee-Yeon KIM, Yuki MIZUTANI, Fumiaki TOYAMA
  • Publication number: 20210225736
    Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Inventors: Jee-Yeon KIM, Kwang-Ho KIM, Fumiaki TOYAMA
  • Patent number: 11011209
    Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 18, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jee-Yeon Kim, Kwang-Ho Kim, Yuki Mizutani, Fumiaki Toyama
  • Publication number: 20210134827
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Inventors: Takaaki IWAI, Hirofumi TOKITA, Yoshitaka OTSU, Fumiaki TOYAMA, Yuki MIZUTANI
  • Patent number: 10991429
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Publication number: 20210098029
    Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Jee-Yeon KIM, Kwang-Ho KIM, Yuki MIZUTANI, Fumiaki TOYAMA
  • Publication number: 20210057336
    Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Shiqian SHAO, Jee-Yeon KIM, Fumiaki TOYAMA, Hirofumi TOKITA
  • Patent number: 10872899
    Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 22, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jee-Yeon Kim, Kwang-Ho Kim, Fumiaki Toyama
  • Patent number: 10861873
    Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 8, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jee-Yeon Kim, Kwang-Ho Kim, Fumiaki Toyama
  • Patent number: 10840260
    Abstract: An alternating stack of insulating layers and dielectric spacer layers is formed over a semiconductor substrate. Memory stack structures are formed through the alternating stack. Backside trenches, a moat trench, and a contact opening are formed through the alternating stack, and are subsequently filled with sacrificial backside trench fill material structures, a sacrificial moat trench fill structure, and a sacrificial contact opening fill structure, respectively. The sacrificial moat trench fill structure is replaced with tubular dielectric wall structure. Portions of the dielectric spacer layers located outside the tubular dielectric wall structure are replaced with electrically conductive layers. The sacrificial backside trench fill material structures are replaced with backside trench fill structures. The sacrificial contact opening fill structure is replaced with a conductive via structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 17, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Murshed Chowdhury, Fumiaki Toyama, Johann Alsmeier, Masaaki Higashitani
  • Publication number: 20200357814
    Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Jee-Yeon KIM, Kwang-Ho KIM, Fumiaki TOYAMA
  • Publication number: 20200357811
    Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Jee-Yeon KIM, Kwang-Ho KIM, Fumiaki TOYAMA
  • Publication number: 20200294599
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Hiroyuki OGAWA, Fumiaki TOYAMA, Takuya ARIKI
  • Patent number: 10726921
    Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Chia-Lin Hsiung, Fumiaki Toyama, Tai-Yuan Tseng, Yan Li
  • Publication number: 20200235120
    Abstract: An alternating stack of insulating layers and dielectric spacer layers is formed over a semiconductor substrate. Memory stack structures are formed through the alternating stack. Backside trenches, a moat trench, and a contact opening are formed through the alternating stack, and are subsequently filled with sacrificial backside trench fill material structures, a sacrificial moat trench fill structure, and a sacrificial contact opening fill structure, respectively. The sacrificial moat trench fill structure is replaced with tubular dielectric wall structure. Portions of the dielectric spacer layers located outside the tubular dielectric wall structure are replaced with electrically conductive layers. The sacrificial backside trench fill material structures are replaced with backside trench fill structures. The sacrificial contact opening fill structure is replaced with a conductive via structure.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Inventors: James KAI, Murshed CHOWDHURY, Fumiaki TOYAMA, Johann ALSMEIER, Masaaki HIGASHITANI
  • Patent number: 10720213
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Publication number: 20200203365
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Inventors: Lishan WENG, Fumiaki TOYAMA, Mohan DUNGA
  • Patent number: 10658381
    Abstract: Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 19, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Fumiaki Toyama, Masaaki Higashitani, Tong Zhang, Chun Ge, Xin Yuan Li, Johann Alsmeier