Patents by Inventor Fumihiko Inoue

Fumihiko Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160073033
    Abstract: An exemplary portable electronic apparatus includes a display provided at a front surface, and an infrared camera and a distance measuring sensor which are provided at a side surface. When a user holds the portable electronic apparatus with their left hand and makes a gesture with their right hand, the portable electronic apparatus analyzes an image from the infrared camera to detect the gesture made by the user. The portable electronic apparatus displays an image corresponding to a result of detection of the gesture on the display.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 10, 2016
    Inventor: Fumihiko INOUE
  • Publication number: 20160059128
    Abstract: A hand-held information processing terminal includes a display, a camera arranged in proximity to the display and capable of obtaining an image of a user including infrared components, an estimation module that estimates relative positional relation between the display and the user based on the obtained image, a generation module that generates a plurality of display images in accordance with the relative positional relation, and a control module that provides stereoscopic display to the user in accordance with a position thereof with the use of the plurality of display images.
    Type: Application
    Filed: July 22, 2015
    Publication date: March 3, 2016
    Inventors: Shinya ITO, Tomohisa KAWAKAMI, Fumihiko INOUE
  • Patent number: 9263249
    Abstract: The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface that is a surface opposing the front surface, step S26 to remove the insulating film formed on the back surface by selectively providing a first chemical on the back surface of the semiconductor wafer, and step S30 to remove the insulating film formed on the front surface by simultaneously immersing the plurality of semiconductor wafers in a second chemical.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: February 16, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Watanabe Tomohiro, Fumihiko Inoue
  • Patent number: 9167231
    Abstract: A first temporary taken image taken by a first imaging section of a stereo imaging section, and a second temporary taken image taken by a second imaging section of the stereo imaging section are displayed on a display section. A user aligns the display position of the first temporary taken image with the display position of the second temporary taken image, by moving the first temporary taken image displayed on the display section. Based on the result of the movement, the display positions of two images composing a stereo image taken with the stereo camera are corrected, and the stereo image is displayed on the display section in a stereoscopically visible manner.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 20, 2015
    Assignee: NINTENDO CO., LTD.
    Inventors: Tomohisa Kawakami, Tsutomu Araki, Takeshi Nishikawa, Fumihiko Inoue, Daigo Shimizu
  • Publication number: 20150253932
    Abstract: An example system includes a housing having at least one surface provided with a display, a linear image sensor located, facing outside the housing, at a side part or a corner part of the housing when the surface provided with the display is viewed as a front surface, and an information processing unit performing information processing based on an image obtained by the linear image sensor.
    Type: Application
    Filed: February 25, 2015
    Publication date: September 10, 2015
    Inventor: Fumihiko INOUE
  • Patent number: 8895405
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: November 25, 2014
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Yukio Hayakawa
  • Patent number: 8815652
    Abstract: The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 26, 2014
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Kentaro Sera
  • Publication number: 20140167211
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 19, 2014
    Applicant: SPANSION LLC
    Inventors: Fumihiko Inoue, Yukio Hayakawa
  • Patent number: 8669606
    Abstract: An embodiment of the invention includes a semiconductor device including a semiconductor substrate with a trench; a tunnel insulating film covering an inner surface of the trench; a trap layer in contact with the tunnel insulating film on an inner surface of an upper portion of the trench; a top insulating film in contact with the trap layer; a gate electrode embedded in the trench, and in contact with the tunnel insulating film at a lower portion of the trench and in contact with the top insulating film at the upper portion of the trench, in which the trap layer and the top insulating film, in between the lower portion of the trench and the upper portion of the trench, extend and protrude from both sides of the trench so as to be embedded in the gate electrode, and a method for manufacturing thereof.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 11, 2014
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Patent number: 8552523
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: October 8, 2013
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Patent number: 8354326
    Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: January 15, 2013
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Takayuki Maruyama, Tomohiro Watanabe
  • Patent number: 8319273
    Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: November 27, 2012
    Assignee: Spansion LLC
    Inventor: Fumihiko Inoue
  • Patent number: 8318566
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 27, 2012
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Haruki Souma, Yukio Hayakawa
  • Publication number: 20120218388
    Abstract: A first temporary taken image taken by a first imaging section of a stereo imaging section, and a second temporary taken image taken by a second imaging section of the stereo imaging section are displayed on a display section. A user aligns the display position of the first temporary taken image with the display position of the second temporary taken image, by moving the first temporary taken image displayed on the display section. Based on the result of the movement, the display positions of two images composing a stereo image taken with the stereo camera are corrected, and the stereo image is displayed on the display section in a stereoscopically visible manner.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: NINTENDO CO., LTD.
    Inventors: Tomohisa KAWAKAMI, Tsutomu Araki, Takeshi Nishikawa, Fumihiko Inoue, Daigo Shimizu
  • Publication number: 20110291227
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.
    Type: Application
    Filed: August 9, 2011
    Publication date: December 1, 2011
    Inventors: Fumiaki TOYAMA, Fumihiko INOUE
  • Publication number: 20110233651
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Application
    Filed: June 8, 2011
    Publication date: September 29, 2011
    Inventors: Fumihiko INOUE, Haruki SOUMA, Yukio HAYAKAWA
  • Publication number: 20110233638
    Abstract: The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.
    Type: Application
    Filed: June 9, 2011
    Publication date: September 29, 2011
    Inventors: Fumiaki TOYAMA, Fumihiko INOUE
  • Patent number: 8003468
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: August 23, 2011
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Haruki Souma, Yukio Hayakawa
  • Publication number: 20110198684
    Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Inventor: Fumihiko INOUE
  • Patent number: 7994007
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 9, 2011
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue