Patents by Inventor Fumihiko Inoue

Fumihiko Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7981746
    Abstract: The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: July 19, 2011
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Patent number: 7932125
    Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: April 26, 2011
    Assignee: Spansion LLC
    Inventor: Fumihiko Inoue
  • Publication number: 20110081767
    Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.
    Type: Application
    Filed: December 6, 2010
    Publication date: April 7, 2011
    Inventors: Fumihiko INOUE, Takayuki MARUYAMA, Tomohiro WATANABE
  • Patent number: 7871896
    Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: January 18, 2011
    Assignee: Spansion, LLC
    Inventors: Fumihiko Inoue, Takayuki Maruyama, Tomohiro Watanabe
  • Patent number: 7838406
    Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 23, 2010
    Assignee: Spansion LLC
    Inventors: Takayuki Maruyama, Fumihiko Inoue
  • Patent number: 7682974
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a top layer (24) as a polysilicon; and etching the etching layer (17) using the mask layer (20) as a mask, and eliminating the top layer (24).
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 23, 2010
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Junpei Yamamoto, Suguru Sassa
  • Publication number: 20100001336
    Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.
    Type: Application
    Filed: December 24, 2008
    Publication date: January 7, 2010
    Inventors: Takayuki MARUYAMA, Fumihiko INOUE
  • Publication number: 20090321812
    Abstract: The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.
    Type: Application
    Filed: December 22, 2008
    Publication date: December 31, 2009
    Inventors: Fumiaki TOYAMA, Fumihiko INOUE
  • Publication number: 20090315098
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.
    Type: Application
    Filed: December 17, 2008
    Publication date: December 24, 2009
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Publication number: 20090206388
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Application
    Filed: August 20, 2008
    Publication date: August 20, 2009
    Inventors: Fumihiko INOUE, Haruki SOUMA, Yukio HAYAKAWA
  • Publication number: 20090032864
    Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 5, 2009
    Inventor: Fumihiko INOUE
  • Publication number: 20090011600
    Abstract: The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface that is a surface opposing the front surface, step S26 to remove the insulating film formed on the back surface by selectively providing a first chemical on the back surface of the semiconductor wafer, and step S30 to remove the insulating film formed on the front surface by simultaneously immersing the plurality of semiconductor wafers in a second chemical.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 8, 2009
    Applicant: Spansion LLC
    Inventors: Watanabe TOMOHIRO, Fumihiko INOUE
  • Publication number: 20090004838
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a top layer (24) as a polysilicon; and etching the etching layer (17) using the mask layer (20) as a mask, and eliminating the top layer (24).
    Type: Application
    Filed: May 30, 2008
    Publication date: January 1, 2009
    Applicant: SPANSION LLC
    Inventors: Fumihiko INOUE, Junpei YAMAMOTO, Suguru SASSA
  • Publication number: 20080316790
    Abstract: The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 25, 2008
    Applicant: SPANSION LLC
    Inventors: Fumihiko Inoue, Kentaro Sera
  • Publication number: 20080305614
    Abstract: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 11, 2008
    Inventors: Fumihiko INOUE, Takayuki MARUYAMA, Tomohiro WATANABE
  • Publication number: 20080166853
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 10, 2008
    Applicant: SPANSION LLC
    Inventors: Fumihiko INOUE, Yukio HAYAKAWA
  • Patent number: 6992010
    Abstract: A method of forming a gate structure. A gate oxide layer, a polysilicon layer, a metallic layer and an insulation layer are sequentially formed over a substrate. Using a definite height level to be an etching end point, the insulation layer, the metallic layer and the polysilicon layer are patterned to form a stack structure. A barrier layer is formed over the stack structure. An etching operation is conducted to form a first spacer covering a portion of each sidewall of the stack structure. The etching operation is continued to remove the polysilicon layer outside the first spacer until the gate oxide layer is exposed. A portion of the exposed polysilicon layer on the sidewalls of the stack structure is removed so that a recess structure is formed. A re-oxidation process is conducted to form a re-oxidation layer within the recess structure. A second spacer is formed over the first spacer and the re-oxidation layer.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: January 31, 2006
    Assignee: Winbond Electronics Corp.
    Inventors: Pao-Haw Chou, Fumihiko Inoue, Toshiro Nakanishi, Yoshio Ozawa
  • Publication number: 20030228766
    Abstract: A method of forming a gate structure. A gate oxide layer, a polysilicon layer, a metallic layer and an insulation layer are sequentially formed over a substrate. Using a definite height level to be an etching end point, the insulation layer, the metallic layer and the polysilicon layer are patterned to form a stack structure. A barrier layer is formed over the stack structure. An etching operation is conducted to form a first spacer covering a portion of each sidewall of the stack structure. The etching operation is continued to remove the polysilicon layer outside the first spacer until the gate oxide layer is exposed. A portion of the exposed polysilicon layer on the sidewalls of the stack structure is removed so that a recess structure is formed. A re-oxidation process is conducted to form a re-oxidation layer within the recess structure. A second spacer is formed over the first spacer and the re-oxidation layer.
    Type: Application
    Filed: February 26, 2003
    Publication date: December 11, 2003
    Inventors: Pao-Haw Chou, Fumihiko Inoue, Toshiro Nakanishi, Yoshio Ozawa
  • Patent number: 6602771
    Abstract: The method for fabricating the semiconductor device comprises the step of: forming a gate insulation film 14 on a semiconductor substrate 10; forming a semiconductor layer 22 containing boron on the gate insulation film 14; forming a silicon nitride film 28 having an Si—H bond concentration in the film immediately after deposited which is below 4.3×1020 cm−3 measured by FT-IR; and patterning the silicon nitride film 28 and the semiconductor layer 22 to form a gate electrode 30 of a semiconductor layer 22 having the upper surface covered by the silicon nitride film 28. Whereby the release of hydrogen in the films in the thermal processing after the silicon nitride film has been formed can be decreased, and the boron penetration from the p-type gate electrode 30p can be suppressed.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 5, 2003
    Assignees: Fujitsu Limited, Kabushiki Kaisha Toshiba
    Inventors: Fumihiko Inoue, Masayuki Tanaka
  • Patent number: 6599794
    Abstract: A method of manufacturing a semiconductor device comprising forming a sacrificial layer including one or more conductive film on a semiconductor substrate, forming a cavity used as a template of electroplating in the sacrificial layer, growing a metal film on a surface of the cavity by the electroplating using the conductive layer as a seed layer so that a cylindrical or convex electrode can be formed, and removing the sacrificial layer so that the electrode can be formed.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 29, 2003
    Assignees: Kabushiki Kaisha Toshiba, Fujitsu Limited
    Inventors: Masahiro Kiyotoshi, Kazuhiro Eguchi, Masaaki Nakabayashi, Fumihiko Inoue