Patents by Inventor Fumihiro Kono
Fumihiro Kono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917826Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: July 19, 2022Date of Patent: February 27, 2024Assignee: Kioxia CorporationInventor: Fumihiro Kono
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Publication number: 20230056494Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.Type: ApplicationFiled: March 15, 2022Publication date: February 23, 2023Applicant: KIOXIA CORPORATIONInventors: Wataru MORIYAMA, Hayato KONNO, Takao NAKAJIMA, Fumihiro KONO, Masaki FUJIU, Kiyoaki IWASA, Tadashi SOMEYA
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Publication number: 20220352205Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: Kioxia CorporationInventor: Fumihiro KONO
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Patent number: 11430805Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: April 20, 2020Date of Patent: August 30, 2022Assignee: Kioxia CorporationInventor: Fumihiro Kono
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Publication number: 20200251493Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Applicant: Toshiba Memory CorporationInventor: Fumihiro KONO
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Patent number: 10672794Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: May 15, 2019Date of Patent: June 2, 2020Assignee: Toshiba Memory CorporationInventor: Fumihiro Kono
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Publication number: 20190267399Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Applicant: Toshiba Memory CorporationInventor: Fumihiro KONO
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Patent number: 10332907Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: February 15, 2018Date of Patent: June 25, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Fumihiro Kono
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Publication number: 20180175058Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Fumihiro Kono
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Patent number: 9929173Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: October 21, 2016Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Fumihiro Kono
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Publication number: 20170040341Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Fumihiro KONO
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Patent number: 9508740Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: January 27, 2016Date of Patent: November 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Fumihiro Kono
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Publication number: 20160141303Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: January 27, 2016Publication date: May 19, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Fumihiro KONO
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Patent number: 9281016Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: June 17, 2014Date of Patent: March 8, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Fumihiro Kono
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Patent number: 8873330Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.Type: GrantFiled: March 12, 2012Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Fumihiro Kono, Kiyotaro Itagaki
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Publication number: 20140293695Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: ApplicationFiled: June 17, 2014Publication date: October 2, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Fumihiro KONO
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Patent number: 8817512Abstract: A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit lines via bit line connection lines. The bit line connection lines have every adjacent N lines (where N is an integer of 2 or more) as one group. The sense amplifiers are arranged in a number smaller than N in a first direction that the bit line connection lines extend. An M number of the sense amplifiers are arranged in a width of a P number of groups in a second direction intersecting the first direction. The M number being larger than the P number.Type: GrantFiled: June 13, 2012Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kono
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Patent number: 8804420Abstract: At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data.Type: GrantFiled: April 27, 2012Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kono
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Publication number: 20140211566Abstract: According to one embodiment, a semiconductor memory device includes a first sense amplifier that is located in a first region and amplifies signals from a memory cell in the first region. A second sense amplifier is located in a second region and amplifies signals from a memory cell in the second region. A bus is connected to the first and second sense amplifiers and passes through the first and second regions. A first latch is located in the second region and is connected to the bus. A second latch is located in the second region and is connected to the bus.Type: ApplicationFiled: August 30, 2013Publication date: July 31, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Fumihiro KONO
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Patent number: 8787061Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.Type: GrantFiled: June 15, 2012Date of Patent: July 22, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kono