Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Abstract: A memory cell array according to an embodiment includes a plurality of NAND strings with a plurality of memory cells stacked, and a bit line is connected to the NAND string. A word line is connected to a gate of the memory cell. A column system circuit is disposed directly under the memory cell array. When viewed from the top side, a global signal supply unit is disposed outside the memory cell array to supply a global signal to the column system circuit. When viewed from the top side, an upper interconnection is disposed over the bit line outside the memory cell array to transmit the global signal. A lower interconnection is disposed under the memory cell array to transmit the global signal to the column system circuit. A contact plug is configured to connect the upper interconnection and the lower interconnection.

Abstract: At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write data to the plural memory cells, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data. The data writing unit stops the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plural memory cells, according to the detection result of the resistance state detecting circuit.

Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.

Abstract: According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information.

Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit lines via bit line connection lines. The bit line connection lines have every adjacent N lines (where N is an integer of 2 or more) as one group. The sense amplifiers are arranged in a number smaller than N in a first direction that the bit line connection lines extend. An M number of the sense amplifiers are arranged in a width of a P number of groups in a second direction intersecting the first direction.

Abstract: According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element.

Abstract: Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a regular periodic external clock signal and generates an internal clock signal. The local clock buffer includes a first signal path that has one or more faster-than-nominal components so that the first rising edge of the internal clock cycle occurs early than it would in a clock buffer with nominal components. When the memory array macro is active for a data access, the local clock buffer stretches a clock cycle of the internal clock signal so that the first and second half-periods of the internal clock cycle are each greater than the half-periods of the external clock signal.

Abstract: According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write data to the plural memory cells, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data. The data writing unit stops the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plural memory cells, according to the detection result of the resistance state detecting circuit.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information.

Abstract: According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element.

Abstract: An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line.

Abstract: Systems and methods for improving a PN ratio of a logic gate by adding a non-switching transistor. In one embodiment, the logic gate includes a plurality of PMOS switching transistors and a plurality of NMOS switching transistors that are switched on and off by received input signals. The PMOS and NMOS switching transistors are interconnected to perform a logic operation on the input signals and produce a corresponding output signal. The non-switching transistor is inserted in the circuit to improve the ratio of PMOS and NMOS transistors between the power nodes of the logic gate. The non-switching transistor is either a PMOS transistor or an NMOS transistor as needed to make the PN ratio closer to 1. The non-switching transistor is biased to keep it switched on and does not affect the logic functions of the gate.

Abstract: Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a regular periodic external clock signal and generates an internal clock signal. The local clock buffer includes a first signal path that has one or more faster-than-nominal components so that the first rising edge of the internal clock cycle occurs early than it would in a clock buffer with nominal components. When the memory array macro is active for a data access, the local clock buffer stretches a clock cycle of the internal clock signal so that the first and second half-periods of the internal clock cycle are each greater than the half-periods of the external clock signal.

Abstract: An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line.

Abstract: A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay.