Patents by Inventor Fumihiro Minami

Fumihiro Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6985055
    Abstract: A transmission line, includes: a first input electrode located in a first level; a plurality of parallel stripe-shaped signal lines in the first level, one end of the signal lines connected to the first input electrode; a first output electrode connected to another end of the signal lines, facing to the first input electrode; a second input electrode adjacent to the first input electrode in a second level facing the first level; a plurality of stripe-shaped ground lines positioned alternately in between and at outer sides of each of the signal lines in the first level, one end of the ground lines connected to the second input electrode; and a second output electrode adjacent to the first output electrode in the second level and connected to another end of the ground lines.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: January 10, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Minami
  • Patent number: 6967288
    Abstract: A shielding wire is provided with a first conductor, a shield for sheathing the first conductor through an insulating member, and a second conductor which is in contact with the shield. Therefore, a troublesome step of unknitting the braid of the shield is eliminated, and the work is done at a higher efficiency and the manufacturing cost is reduced.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: November 22, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ohsawa, Fumihiro Minami, Mutsuo Sekiya
  • Patent number: 6867673
    Abstract: Providing a high-voltage-side terminal with means for preventing a core inserted into a central hole of a bobbin from getting out of position securely fixes the core to the predetermined position, at the time a transformer which is a part of an ignitor is assembled, during the work proceeds from the inserting step of the core to the next step. Thus, at the time the ignitor-integral type bulb socket is assembled, the core hardly moves out of the predetermined position and there is a less possibility that the core gets out of position. Accordingly, this does not require so high machining accuracy of both members and reduces the cost for machining the product as well as for inspecting the dimension control or the like.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: March 15, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumihiro Minami, Mutsuo Sekiya, Masaru Kibi
  • Publication number: 20050017653
    Abstract: A through hole that is slightly larger than a size of a rear end of a transformer container is formed in a rear cover constituting a part of an external wall of a starting circuit unit. The transformer container houses therein a transformer and constitutes a transformer portion. The transformer portion is assembled such that a rear end of the transformer container projects from the through hole. This allows the transformer container to constitute a part of the external wall of the starting circuit unit.
    Type: Application
    Filed: July 21, 2004
    Publication date: January 27, 2005
    Inventors: Fumihiro Minami, Takashi Ohsawa, Kinsho Ando
  • Publication number: 20040237060
    Abstract: A clock layout method comprises accepting circuit information on a logic circuit, placing a route driver on a semiconductor chip and forming initial clock routing with an H-tree structure in a local area and with a star structure in a global area, specifying a second node which first appears on a first wire among a plurality of wires branching from an arbitrary first node in the initial clock routing, specifying at least a third node which is the second to appear on a wire other than the first wire among the plurality of wires branching from the first node, defining the defined third node which exists in a direction within a predetermined angle from an input direction of a signal inputted to the second node, among the third nodes, folding a wire from the first node up to the defined third node and a node present therebetween.
    Type: Application
    Filed: March 18, 2004
    Publication date: November 25, 2004
    Inventors: Mutsunori Igarashi, Fumihiro Minami
  • Patent number: 6813756
    Abstract: With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: November 2, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka
  • Publication number: 20040183103
    Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 23, 2004
    Inventors: Naohito Kojima, Fumihiro Minami, Kimiyoshi Usami
  • Publication number: 20040090282
    Abstract: A transmission line, includes: a first input electrode located in a first level; a plurality of parallel stripe-shaped signal lines in the first level, one end of the signal lines connected to the first input electrode; a first output electrode connected to another end of the signal lines, facing to the first input electrode; a second input electrode adjacent to the first input electrode in a second level facing the first level; a plurality of stripe-shaped ground lines positioned alternately in between and at outer sides of each of the signal lines in the first level, one end of the ground lines connected to the second input electrode; and a second output electrode adjacent to the first output electrode in the second level and connected to another end of the ground lines.
    Type: Application
    Filed: April 1, 2003
    Publication date: May 13, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Minami
  • Patent number: 6714483
    Abstract: An inclination angle measurement apparatus includes a first ultrasonic sensor (3) for sending an ultrasonic wave toward a road surface (2), second and third ultrasonic sensors (4 and 5) each for receiving an ultrasonic wave reflected from the road surface (2), and a calculation control circuit (14) for calculating an angle of inclination of a vehicle with respect to the road surface (2) based on a phase difference between ultrasonic waves received by the second and third ultrasonic sensors (4 and 5). Thus the inclination angle measurement apparatus can accurately measure the angle of inclination of the vehicle with respect to the road surface (2).
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: March 30, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumihiro Minami, Takashi Ohsawa, Yoshio Katayama
  • Patent number: 6688917
    Abstract: An integral connector in which a power input connector and a power output connector are integrated with each other is disposed on a base plate.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: February 10, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroki Ushio, Fumihiro Minami
  • Patent number: 6668363
    Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 23, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Minami, Takeshi Kitahara, Kimiyoshi Usami, Seiichi Nishio
  • Patent number: 6645842
    Abstract: There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: November 11, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Takashi Mitsuhashi, Masami Murakata, Masaaki Yamada, Fumihiro Minami, Toshihiro Akiyama, Takahiro Aoki
  • Publication number: 20030156585
    Abstract: An inclination angle measurement apparatus includes a first ultrasonic sensor (3) for sending an ultrasonic wave toward a road surface (2), second and third ultrasonic sensors (4 and 5) each for receiving an ultrasonic wave reflected from the road surface (2), and a calculation control circuit (14) for calculating an angle of inclination of a vehicle with respect to the road surface (2) based on a phase difference between ultrasonic waves received by the second and third ultrasonic sensors (4 and 5). Thus the inclination angle measurement apparatus can accurately measure the angle of inclination of the vehicle with respect to the road surface (2).
    Type: Application
    Filed: February 5, 2003
    Publication date: August 21, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Fumihiro Minami, Takashi Ohsawa, Yoshio Katayama
  • Publication number: 20030082953
    Abstract: An integral connector in which a power input connector and a power output connector are integrated with each other is disposed on a base plate.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 1, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroki Ushio, Fumihiro Minami
  • Publication number: 20030079194
    Abstract: With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.
    Type: Application
    Filed: October 24, 2002
    Publication date: April 24, 2003
    Inventors: Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka
  • Patent number: 6546540
    Abstract: With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: April 8, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka
  • Publication number: 20030014724
    Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 16, 2003
    Inventors: Naohito Kojima, Fumihiro Minami, Masami Murakata, Takashi Ishioka
  • Publication number: 20020182844
    Abstract: There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost.
    Type: Application
    Filed: July 18, 2002
    Publication date: December 5, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsunori Igarashi, Takashi Mitsuhashi, Masami Murakata, Masaaki Yamada, Fumihiro Minami, Toshihiro Akiyama, Takahiro Aoki
  • Publication number: 20020171527
    Abstract: Providing a high-voltage-side terminal with means for preventing a core inserted into a central hole of a bobbin from getting out of position securely fixes the core to the predetermined position, at the time a transformer which is a part of an ignitor is assembled, during the work proceeds from the inserting step of the core to the next step. Thus, at the time the ignitor-integral type bulb socket is assembled, the core hardly moves out of the predetermined position and there is a less possibility that the core gets out of position. Accordingly, this does not require so high machining accuracy of both members and reduces the cost for machining the product as well as for inspecting the dimension control or the like.
    Type: Application
    Filed: April 17, 2002
    Publication date: November 21, 2002
    Inventors: Fumihiro Minami, Mutsuo Sekiya, Masaru Kibi
  • Publication number: 20020155738
    Abstract: A shielding wire is provided with a first conductor, a shield for sheathing the first conductor through an insulating member, and a second conductor which is in contact with the shield. Therefore, a troublesome step of unknitting the braid of the shield is eliminated, and the work is done at a higher efficiency and the manufacturing cost is reduced.
    Type: Application
    Filed: April 16, 2002
    Publication date: October 24, 2002
    Inventors: Takashi Ohsawa, Fumihiro Minami, Mutsuo Sekiya