Abstract: A mounting board has a board, retaining members mounted on the upper surface of the board, and a part retained by the retaining members. The part is mounted such that at least a part thereof is arranged below the lower surface of the board, and that the part is electrically connected to the board through the retaining members. Such an arrangement as described above eliminates the need of connecting the discharge gap element to the board by using lead wires, and of mounting it on the upper surface of the board. This lowers the height of the board and admits an elevated part.

Abstract: There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost.

Abstract: An electric discharge lamp lighting device wherein a high voltage generating transformer 10 comprises a secondary coil 13 wound on an outer side of a laminated core 12 disposed in the center of a bobbin 11 and a primary coil 14 wound on an outer side of said secondary coil 13. A high voltage output terminal 13a of said secondary coil 13 is connected to a high voltage terminal of an HID lamp through a terminal 12a of a laminated core 12. A low voltage input terminal 13b of said secondary coil 13 is connected to a primary coil 14. As a result, insulation volume can be reduced and a reduction in the size of the device can be achieved.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: A lamp socket has a socket body with a plugging section in which a lamp plug is removably plugged. In the plugging section, there are a central terminal and a side terminal. An insulation seal member provides electrical isolation between the central terminal and the side terminal and is prevented from dislodging when the lamp plug is removed from the socket body by forming a structure from at least one of the central terminal and the insulation seal member which are adapted to fit into one another. Thus, the removal of the insulation seal member when the lamp plug is plugged out of the socket body can be prevented by the central terminal of the socket body and/or the insulation seal member itself. Therefore, there is no need to install an additional component such as a stopper. Thus, the number of components and its manufacturing cost can be reduced compared with a conventional lamp socket.

Abstract: There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost.

Abstract: A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.

Abstract: A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.

Abstract: A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells.

Abstract: A clock-signal distributing method used in a wiring-pattern network such that a clock signal is supplied from root driver cells via repeating buffer cells to terminal cells.

Abstract: A computer-assisted automatic wiring method is presented for logic LSI substrates wherein channel boundary terminals are defined on the boundary line of the first and second channels forming a T-shaped crossing region between the function blocks arranged on a substrate after global wiring process. These channel boundary terminals are roughly divided into the first and second terminal groups there may remain channel boundary terminals which do not belong to any one of the groups. The first terminal group includes terminals intersecting wirings which tend to run along the first direction in the second channel, which corresponds to a top bar of the letter "T". The second terminal group includes terminals intersecting wirings which have tend to run along the second direction opposite to the first direction in said second channel. A pair of channel boundary terminals is sequentially selected from the first and second groups.