Abstract: Provided is an antenna-equipped semiconductor package which is excellent in solder heat resistance and has low transmission loss. In the antenna-equipped semiconductor package 100 in which an antenna unit 5 is integrally formed in a semiconductor device unit 10, at least one of an insulating layer 1 for connecting the semiconductor device unit 10 and the antenna unit 5 and an insulating layer 1 inside the antenna unit is a cured product of a resin composition including (A) a styrene-based elastomer having a double bond and (B) a compound generating a radical.

Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

Abstract: A circuit device includes an A/D converter circuit that performs A/D conversion by successive approximation using a charge redistribution type D/A converter circuit having capacitor array circuits on the positive electrode side and the negative electrode side, and quantization error hold circuits that hold charges corresponding to a quantization error in the A/D conversion. The quantization error hold circuits include quantization error hold circuits on the positive electrode side and the negative electrode side having one ends connected to sampling nodes of the capacitor array circuits on the positive electrode side and the negative electrode side. The quantization error hold circuits on the positive electrode side and the negative electrode side are placed on a second direction side orthogonal to a first direction in which the capacitor array circuits on the positive electrode side and the negative electrode side are placed.

Abstract: A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.

Abstract: An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Abstract: A resonator device includes a first resonator that generates a reference clock signal, a second resonator that generates a first clock signal having a frequency adjusted based on the reference clock signal, and a circuit device that includes a temperature sensor for performing temperature compensation on an oscillation frequency of the first resonator. The temperature sensor is disposed on the circuit device such that the first resonator overlaps the temperature sensor in a plan view.

Abstract: A resonator device includes first and second resonators and an integrated circuit. The integrated circuit includes first and second oscillation circuits that oscillate first and second resonators, first and second terminals connected to the first oscillation circuit, and third and fourth terminals connected to the second oscillation circuit. The first terminal of the integrated circuit and one electrode of the first resonator are connected to each other via a bump. The third terminal and one electrode of the second resonator are connected to each other via a bump. In a plan view, at least a portion of the first resonator overlaps the first oscillation circuit and at least a portion of the second resonator overlaps the second oscillation circuit.

Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

Abstract: An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.

Abstract: A circuit device includes an A/D converter circuit that performs A/D conversion by successive approximation using a charge redistribution type D/A converter circuit having capacitor array circuits on the positive electrode side and the negative electrode side, and quantization error hold circuits that hold charges corresponding to a quantization error in the A/D conversion. The quantization error hold circuits include quantization error hold circuits on the positive electrode side and the negative electrode side having one ends connected to sampling nodes of the capacitor array circuits on the positive electrode side and the negative electrode side. The quantization error hold circuits on the positive electrode side and the negative electrode side are placed on a second direction side orthogonal to a first direction in which the capacitor array circuits on the positive electrode side and the negative electrode side are placed.

Abstract: Provided is a resin composition for a film, which is used for producing the film having excellent insulating properties and thermal conductivity. The provided resin composition for the film contains a thermosetting resin (A) and hexagonal boron nitride secondary agglomerated particles (B). Here, the hexagonal boron nitride secondary agglomerated particles (B) contains hexagonal boron nitride secondary agglomerated particles (B-1) having a cohesive breaking strength of 7 MPa or more and hexagonal boron nitride secondary agglomerated particles (B-2) having a cohesive breaking strength of 3 MPa or more and less than 7 MPa.

Abstract: An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.

Abstract: A resonator device includes a first resonator that generates a reference clock signal, a second resonator that generates a first clock signal having a frequency adjusted based on the reference clock signal, and a circuit device that includes a temperature sensor for performing temperature compensation on an oscillation frequency of the first resonator. The temperature sensor is disposed on the circuit device such that the first resonator overlaps the temperature sensor in a plan view.

Abstract: An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Abstract: A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.

Abstract: A resonator device includes first and second resonators and an integrated circuit. The integrated circuit includes first and second oscillation circuits that oscillate first and second resonators, first and second terminals connected to the first oscillation circuit, and third and fourth terminals connected to the second oscillation circuit. The first terminal of the integrated circuit and one electrode of the first resonator are connected to each other via a bump. The third terminal and one electrode of the second resonator are connected to each other via a bump. In a plan view, at least a portion of the first resonator overlaps the first oscillation circuit and at least a portion of the second resonator overlaps the second oscillation circuit.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.

Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Abstract: A display driver includes an interface circuit block which is disposed in a second area AR2 of first to third areas AR1 to AR3 and transfers data through a serial bus using differential signals when a direction from a first side L1 which is a short side of the display driver to a third side L3 opposite to the first side L1 is defined as a first direction DR1, a direction from a fourth side L4 which is a long side of the display driver to a second side L2 opposite to the fourth side L4 is defined as a second direction DR2, and areas created by dividing the long side of the display driver into three portions along the first direction DR1 are defined as first to third areas AR1 to AR3 in that order, the interface circuit block including an input terminal formation area in which a plurality of input terminals PAD are formed, the input terminal formation area being disposed in the interface circuit block on the second side L2.

Abstract: A host controller includes a disconnection detection circuit 52 which compares a voltage level of a first differential signal DP of first and second differential signals DP and DM making up a differential signal pair corresponding to a given range in a frame packet with a comparison voltage CV, compares a voltage level of the second differential signal DM corresponding to a given range in the frame packet with the comparison voltage CV, and detects that a host and a device have been disconnected when the voltage level of at least one of the first and second differential signals DP and DM corresponding to the given range is higher than the comparison voltage CV.