Abstract: An integrated circuit device includes: first through fourth terminals arranged in order in which the first terminal and the fourth terminal are arranged in line symmetry with respect to a center axis of the first through fourth terminals, and the second terminal and the third terminal are arranged in line symmetry with respect to the center axis; a first receiving circuit coupled to the first and second terminals, the first receiving circuit receiving one of a first differential signal pair and a second differential signal pair; a second receiving circuit coupled to the third and fourth terminals, the second receiving circuit receiving the first differential signal pair when the first receiving circuit receives the second differential signal pair and the second differential signal pair when the first receiving circuit receives the first differential signal pair; a first selector selecting one of a first signal and a second signal obtained by inverting the first signal that are output from the first receiving

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: An integrated circuit device 10 includes an interface circuit block 120, wherein, when a direction from a first side LS1 which is a short side of the interface circuit block 120 to a third side LS3 opposite to the first side LS1 is defined as a first direction DR1 and a direction from a fourth side LS4 which is a long side of the interface circuit block 120 to a second side LS2 opposite to the fourth side LS4 is defined as a second direction DR2, the interface circuit block 120 includes a circuit formation area 122 in which a circuit which performs given processing is formed, an input terminal formation area 124 which is disposed on a side of the circuit formation area 122 in the second direction DR2 and in which a plurality of input terminals PAD are provided on the second side LS2 along the first direction DR1, and a plurality of power supply lines DRVSS and DRVDD1 to DRVDD3 for the integrated circuit device 10 formed to extend along the first direction DR1 in the input terminal formation area 124 in an int

Abstract: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are formed in a P-type transistor area ARP1, a transistor NT1 of the first transmission driver and a transistor NT3 of the third transmission driver are formed in an N-type transistor area ARN1, a transistor PT2 of the second transmission driver and a transistor PT4 of the fourth transmission driver are formed in a P-type transistor area ARP2, and a transistor NT2 of the second transmission driver and a transistor NT4 of the fourth transmission driver are formed in an N-type transistor area ARN2.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. The high-speed I/F circuit block includes a physical layer circuit including a receiver circuit, and a high-speed I/F logic circuit including a serial/parallel conversion circuit. The high-speed I/F circuit block is disposed so that the high-speed I/F logic circuit is disposed between the physical layer circuit and the driver logic circuit block and the physical layer circuit and the driver logic circuit block are not adjacently disposed.

Abstract: An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receiving circuit receiving the pair of differential signals that are input from the input pad region, wherein the first power supply input region and the second power supply input region are disposed in a direction along one side of the interface circuit so as to sandwich the differential signal input region.

Abstract: Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nth resistance elements, where N is an integral number equal to or more than 2, and a first to an nth cut-off elements connected in serial with each of the corresponding n(1?n<N) first to the Nth resistance elements of the first to the Nth resistance elements.

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: Providing a transmission circuit, which can transfer data normally with high speed even toward a host controller and a device, which does not meet design requirements defined in the standard, a data-transfer control device and electronic equipment. A current source coupled between a first source VDD and a node ND10; a first transistor SW1 formed between the node ND10 and a DP terminal; a second transistor SW2 formed between the node ND10 and a DM terminal; a first buffers outputting a first control signal HS_DPout 2 to the gate of the first transistor SW1; and a second buffer outputting a second control signal HS_DMout 2 to the gate of the second transistor SW2; are included. When any of the first control signal HS_DPout2 and the second control signal HS_Dmout 2 is set active, other of the control signals is set non-active. Each of the buffers includes a first inverter INV1 and a second inverter INV receiving an output from the first inverter INV1.

Abstract: A receptacle which is defined in a given interface standard, performs data transfer by using differential signals, and is connected to a plug when transmitting a signal between devices. The receptacle includes: a power supply terminal; a ground terminal; a first differential signal terminal used for transmitting a first differential signal; a second differential signal terminal used for transmitting a second differential signal, the second differential signal terminal making a pair with the first differential signal terminal; and at least one protection element provided between the power supply terminal and the ground terminal.

Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Abstract: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are formed in a P-type transistor area ARP1, a transistor NT1 of the first transmission driver and a transistor NT3 of the third transmission driver are formed in an N-type transistor area ARN1, a transistor PT2 of the second transmission driver and a transistor PT4 of the fourth transmission driver are formed in a P-type transistor area ARP2, and a transistor NT2 of the second transmission driver and a transistor NT4 of the fourth transmission driver are formed in an N-type transistor area ARN2.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. The high-speed I/F circuit block includes a physical layer circuit including a receiver circuit, and a high-speed I/F logic circuit including a serial/parallel conversion circuit. The high-speed I/F circuit block is disposed so that the high-speed I/F logic circuit is disposed between the physical layer circuit and the driver logic circuit block and the physical layer circuit and the driver logic circuit block are not adjacently disposed.

Abstract: An integrated circuit device includes: first through fourth terminals arranged in order in which the first terminal and the fourth terminal are arranged in line symmetry with respect to a center axis of the first through fourth terminals, and the second terminal and the third terminal are arranged in line symmetry with respect to the center axis; a first receiving circuit coupled to the first and second terminals, the first receiving circuit receiving one of a first differential signal pair and a second differential signal pair; a second receiving circuit coupled to the third and fourth terminals, the second receiving circuit receiving the first differential signal pair when the first receiving circuit receives the second differential signal pair and the second differential signal pair when the first receiving circuit receives the first differential signal pair; a first selector selecting one of a first signal and a second signal obtained by inverting the first signal that are output from the first receiving

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.

Abstract: A host controller includes a disconnection detection circuit 52 which compares a voltage level of a first differential signal DP of first and second differential signals DP and DM making up a differential signal pair corresponding to a given range in a frame packet with a comparison voltage CV, compares a voltage level of the second differential signal DM corresponding to a given range in the frame packet with the comparison voltage CV, and detects that a host and a device have been disconnected when the voltage level of at least one of the first and second differential signals DP and DM corresponding to the given range is higher than the comparison voltage CV.

Abstract: Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nth resistance elements, where N is an integral number equal to or more than 2, and a first to an nth cut-off elements connected in serial with each of the corresponding n(1?n<N) first to the Nth resistance elements of the first to the Nth resistance elements.

Abstract: An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receiving circuit receiving the pair of differential signals that are input from the input pad region, wherein the first power supply input region and the second power supply input region are disposed in a direction along one side of the interface circuit so as to sandwich the differential signal input region.

Abstract: A display driver includes an interface circuit block which is disposed in a second area AR2 of first to third areas AR1 to AR3 and transfers data through a serial bus using differential signals when a direction from a first side L1 which is a short side of the display driver to a third side L3 opposite to the first side L1 is defined as a first direction DR1, a direction from a fourth side L4 which is a long side of the display driver to a second side L2 opposite to the fourth side L4 is defined as a second direction DR2, and areas created by dividing the long side of the display driver into three portions along the first direction DR1 are defined as first to third areas AR1 to AR3 in that order, the interface circuit block including an input terminal formation area in which a plurality of input terminals PAD are formed, the input terminal formation area being disposed in the interface circuit block on the second side L2.