Abstract: An integrated circuit device 10 includes an interface circuit block 120, wherein, when a direction from a first side LS1 which is a short side of the interface circuit block 120 to a third side LS3 opposite to the first side LS1 is defined as a first direction DR1 and a direction from a fourth side LS4 which is a long side of the interface circuit block 120 to a second side LS2 opposite to the fourth side LS4 is defined as a second direction DR2, the interface circuit block 120 includes a circuit formation area 122 in which a circuit which performs given processing is formed, an input terminal formation area 124 which is disposed on a side of the circuit formation area 122 in the second direction DR2 and in which a plurality of input terminals PAD are provided on the second side LS2 along the first direction DR1, and a plurality of power supply lines DRVSS and DRVDD1 to DRVDD3 for the integrated circuit device 10 formed to extend along the first direction DR1 in the input terminal formation area 124 in an int

Abstract: Providing a transmission circuit, which can transfer data normally with high speed even toward a host controller and a device, which does not meet design requirements defined in the standard, a data-transfer control device and electronic equipment. A current source coupled between a first source VDD and a node ND10; a first transistor SW1 formed between the node ND10 and a DP terminal; a second transistor SW2 formed between the node ND10 and a DM terminal; a first buffers outputting a first control signal HS_DPout 2 to the gate of the first transistor SW1; and a second buffer outputting a second control signal HS_DMout 2 to the gate of the second transistor SW2; are included. When any of the first control signal HS_DPout2 and the second control signal HS_Dmout 2 is set active, other of the control signals is set nonnative. Each of the buffers includes a first inverter INV1 and a second inverter INV receiving an output from the first inverter INV1.

Abstract: A receptacle which is defined in a given interface standard, performs data transfer by using differential signals, and is connected to a plug when transmitting a signal between devices. The receptacle includes: a power supply terminal; a ground terminal; a first differential signal terminal used for transmitting a first differential signal; a second differential signal terminal used for transmitting a second differential signal, the second differential signal terminal making a pair with the first differential signal terminal; and at least one protection element provided between the power supply terminal and the ground terminal.

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: A macrocell MC1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O region IOR1 along a side SD1; and power terminals PVDD, PVSS, XVDD, and XVSS and clock terminals XI and XO of a clock generation circuit and a sampling clock circuit are placed in an I/O region IOR2 along a side SD2. An interface region and a macrocell MC2 including user-specified logic are provided along a side SD3. A reception circuit is placed on a DR1 side of IOR1, a clock generation circuit is placed on a DR2 side of IOR2, and a sampling clock generation circuit is placed on the DR1 side of the reception circuit and also the DR2 side of the clock generation circuit. A transmission circuit is placed on the DR2 side of the reception circuit and on the DR1 side of the data terminals DP and DM.

Abstract: A macrocell MC1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O region IOR1 along a side SD1; and power terminals PVDD, PVSS, XVDD, and XVSS and clock terminals XI and XO of a clock generation circuit and a sampling clock circuit are placed in an I/O region IOR2 along a side SD2. An interface region and a macrocell MC2 including user-specified logic are provided along a side SD3. A reception circuit is placed on a DR1 side of IOR1, a clock generation circuit is placed on a DR2 side of IOR2, and a sampling clock generation circuit is placed on the DR1 side of the reception circuit and also the DR2 side of the clock generation circuit. A transmission circuit is placed on the DR2 side of the reception circuit and on the DR1 side of the data terminals DP and DM.