Patents by Inventor Fumio Echigo

Fumio Echigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8395056
    Abstract: A multilayer printed wiring board (11) is composed of a plurality of printed wiring boards (21a and 21b) each having wiring on its both sides, and a relaxing connection layer (15) for interconnecting the printed wiring boards (21a and 21b). The relaxing connection layer (15) contains an inorganic filler, a thermosetting resin, and a reliever for relieving internal stress. The multilayer printed wiring board (11) is prevented from warpage by making the relaxing connection layer (15) disposed inside it absorb internal stress caused by heating and cooling in a solder reflow process or other processes.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Tadashi Nakamura, Fumio Echigo, Masaaki Katsumata
  • Patent number: 8134082
    Abstract: A solid printed circuit board is manufactured by bonding upper and lower printed circuit boards having different shapes and provided with wirings formed on surfaces thereof. A bonding layer is made of insulating material containing thermosetting resin and inorganic filler dispersed therein, and has a via-conductor made of conductive paste filling a through-hole perforated in a predetermined position of the bonding layer. This circuit board provides a packaging configuration achieving small size and thickness and three-dimensional mounting suitable for semiconductors of high performance and multiple-pin structure.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 13, 2012
    Assignee: Panasonic Corporation
    Inventors: Tadashi Nakamura, Fumio Echigo, Takayuki Kita, Kota Fukasawa, Shogo Hirai
  • Patent number: 8076589
    Abstract: A multilayer wiring board employs a thin insulating substrate having substantially only resin flow as the compression property effect, and has an any-layer IVH structure where at least one core layer is formed without burying wiring. For sufficiently securing an effective compression amount of the crush-allowance of a conductor, the ratio of the thickness of a cover film to that of the electrical insulating substrate is increased, and a via can be formed in the core layer without burying the wiring in the insulating substrate. Thus, a multilayer wiring board having an any-layer IVH structure that can achieve high-density component mountability and wiring storability in an extremely small thickness can be provided.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: December 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Tadashi Nakamura, Fumio Echigo, Shogo Hirai
  • Patent number: 7956293
    Abstract: A multilayer printed wiring board is characterized in that the interlayer connection material in the via holes has a lower coefficient of thermal expansion in the thickness direction than the electrically insulating substrate made of insulating material; the interlayer connection is formed at a temperature higher than the operating temperature; and the interlayer connection material is larger in thickness than the interlayer connection material of the same wiring layer at normal temperature. This causes a difference in the coefficient of thermal expansion between the different materials in the thickness direction of the printed wiring board in the environment in which it is used resulting in high connection reliability.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: June 7, 2011
    Assignee: Panasonic Corporation
    Inventors: Fumio Echigo, Shogo Hirai, Tadashi Nakamura
  • Publication number: 20110030207
    Abstract: A multilayer printed wiring board is characterized in that the interlayer connection material in the via holes has a lower coefficient of thermal expansion in the thickness direction than the electrically insulating substrate made of insulating material; the interlayer connection is formed at a temperature higher than the operating temperature; and the interlayer connection material is larger in thickness than the interlayer connection material of the same wiring layer at normal temperature. This causes a difference in the coefficient of thermal expansion between the different materials in the thickness direction of the printed wiring board in the environment in which it is used resulting in high connection reliability.
    Type: Application
    Filed: October 19, 2010
    Publication date: February 10, 2011
    Applicant: Panasonic Corporation
    Inventors: Fumio ECHIGO, Shogo HIRAI, Tadashi NAKAMURA
  • Publication number: 20100276187
    Abstract: A multilayer printed wiring board (11) is composed of a plurality of printed wiring boards (21a and 21b) each having wiring on its both sides, and a relaxing connection layer (15) for interconnecting the printed wiring boards (21a and 21b). The relaxing connection layer (15) contains an inorganic filler, a thermosetting resin, and a reliever for relieving internal stress. The multilayer printed wiring board (11) is prevented from warpage by making the relaxing connection layer (15) disposed inside it absorb internal stress caused by heating and cooling in a solder reflow process or other processes.
    Type: Application
    Filed: January 16, 2009
    Publication date: November 4, 2010
    Inventors: Tadashi Nakamura, Fumio Echigo, Masaaki Katsumata
  • Publication number: 20100230138
    Abstract: A wiring board includes an insulating board having a top surface arranged to have an electronic component mounted thereto, a conductor pattern formed on the top surface of the insulating board, and a heat emitting layer made of heat-emitting material covering the conductor pattern. The heat-emitting material has an emissivity not less than 0.8 for an electromagnetic wave having a wavelength ?=0.002898/T at a temperature T ranging from 293K to 473K. This wiring board suppresses the temperature rise of the electronic component.
    Type: Application
    Filed: March 26, 2008
    Publication date: September 16, 2010
    Inventors: Toshiyuki Asahi, Yukihiro Shimasaki, Fumio Echigo
  • Publication number: 20100170700
    Abstract: A solid printed circuit board is manufactured by bonding upper and lower printed circuit boards having different shapes and provided with wirings formed on surfaces thereof. A bonding layer is made of insulating material containing thermosetting resin and inorganic filler dispersed therein, and has a via-conductor made of conductive paste filling a through-hole perforated in a predetermined position of the bonding layer. This circuit board provides a packaging configuration achieving small size and thickness and three-dimensional mounting suitable for semiconductors of high performance and multiple-pin structure.
    Type: Application
    Filed: May 28, 2008
    Publication date: July 8, 2010
    Applicant: Panasonic Corporation
    Inventors: Tadashi Nakamura, Fumio Echigo, Takayuki Kita, Kota Fukasawa, Shogo Hirai
  • Publication number: 20090229862
    Abstract: A plurality of double-sided boards using a film are attached to each other with a paste coupling layer sandwiched therebetween. In the paste coupling layer, a conductive paste is filled into a through hole formed in provisionally hardened resin, which is hardened. At the same time, second wirings are electrically coupled to each other by using the hardened conductive paste filled in the through holes that have been previously formed in the paste coupling layer. Thus, it is possible to provide a thinned multilayer printed wiring board without using an adhesive.
    Type: Application
    Filed: November 7, 2006
    Publication date: September 17, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tadashi Nakamura, Fumio Echigo, Shogo Hirai, Toshio Sugawa
  • Publication number: 20090139761
    Abstract: A multilayer printed wiring board is characterized in that the interlayer connection material in the via holes has a lower coefficient of thermal expansion in the thickness direction than the electrically insulating substrate made of insulating material; the interlayer connection is formed at a temperature higher than the operating temperature; and the interlayer connection material is larger in thickness than the interlayer connection material of the same wiring layer at normal temperature. This causes a difference in the coefficient of thermal expansion between the different materials in the thickness direction of the printed wiring board in the environment in which it is used resulting in high connection reliability.
    Type: Application
    Filed: April 2, 2007
    Publication date: June 4, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Fumio Echigo, Shogo Hirai, Tadashi Nakamura
  • Publication number: 20080308304
    Abstract: A multilayer wiring board employs a thin insulating substrate having substantially only resin flow as the compression property effect, and has an any-layer IVH structure where at least one core layer is formed without burying wiring. For sufficiently securing an effective compression amount of the crush-allowance of a conductor, the ratio of the thickness of a cover film to that of the electrical insulating substrate is increased, and a via can be formed in the core layer without burying the wiring in the insulating substrate. Thus, a multilayer wiring board having an any-layer IVH structure that can achieve high-density component mountability and wiring storability in an extremely small thickness can be provided.
    Type: Application
    Filed: April 26, 2006
    Publication date: December 18, 2008
    Inventors: Tadashi Nakamura, Fumio Echigo, Shogo Hirai
  • Publication number: 20080121416
    Abstract: In a case of multilayer circuit boards where a plurality of conventional films are used as insulating layers, the films are connected with each other using an adhesive, and therefore, the adhesive sometimes negatively affects reduction in thickness. Therefore, a plurality of two-sided boards with films used therein are pasted together with a paste connection layer interposed therebetween, the paste connection layer being configured such that through holes formed in a prepreg are filled in with a conductive paste which is then cured, and second wires are electrically connected with each other through the conductive paste with which the through holes formed in the paste connection layer in advance are filled in, and thus, a multilayer board can be provided without using an adhesive, and the entirety of the multilayer circuit board can be reduced in thickness.
    Type: Application
    Filed: October 19, 2006
    Publication date: May 29, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shogo Hirai, Fumio Echigo, Tadashi Nakamura, Toshio Sugawa
  • Patent number: 7174632
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 7155820
    Abstract: The present invention provides a method of manufacturing a printed circuit board, which includes preparing a dielectric substrate, coating surfaces of the dielectric substrate, filling a via hole with a conductor, peeling mold-releasing films, compressing the dielectric substrate and forming metal foils. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: January 2, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Publication number: 20060283626
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 21, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 7132029
    Abstract: It is an object of the present invention to provide a multilayer circuit board, and a method for manufacturing the same, in which a plurality of circuit boards are layered, wherein as regards at least one circuit board positioned on an outer side, a conductive substance is filled into holes passing through the circuit board in the thickness direction and cured, and the wiring layers of the plurality of circuit boards are electrically connected by the conductive substance that has been cured, wherein in the multilayer circuit board, the wiring layer positioned outside the conductive substance that has been cured projects outward from its surroundings. Thus, the conductive paste is sufficiently compressed during hot pressing to yield a stable electrical connection, and thermosetting resin can be filled in between the inner layer wiring pattern without leaving gaps.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: November 7, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Nakatani, Hideki Higashitani, Tadashi Nakamura, Fumio Echigo
  • Patent number: 7103971
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: September 12, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 7066344
    Abstract: A mask film includes a base material, a parting layer and a non-parting portion placed on the base material. Accordingly, an optimum adhesion strength of the mask film and a prepreg sheet can be maintained, and peeling between the mask film and prepreg sheet can be prevented. Further, by preventing the fusing adhesion between the mask film and prepreg sheet due to heat generated when forming penetration holes, a circuit board having an excellent quality is obtained.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: June 27, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiaki Takenaka, Toshikazu Kondo, Kunio Kishimoto, Shinji Nakamura, Fumio Echigo
  • Patent number: 7047629
    Abstract: A circuit board manufacturing method including the steps of forming a through hole on an insulator layer and then filling the through hole with a conductive paste; dispersing and forming a protective agent on an adhesion surface of a conductor foil so as to include adhesion surface regions where the protective agent does not exist; sticking the conductor foil to the insulator layer; and abutting a plurality of conductive powders constituting the conductive paste and the conductor foil to each other through the adhesion surface regions by means of heating and pressurizing the insulator layer and conductor foil.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 7045198
    Abstract: The present invention provides a prepreg and a circuit board that can achieve, e.g., low interstitial via connection resistance, excellent connection stability, and high durability, regardless of materials, physical properties, and a combination of the materials of an insulating layer. The present invention also provides a method for manufacturing the prepreg and the circuit board. The prepreg of the present invention includes a laminate including at least one first layer and at least one second layer. The first layer is an insulating layer that includes a resin. The second layer has pores that connect an upper and a lower surface of the second layer, and the upper and the lower surface of the second layer differ from each other in at least one selected from open are ratio and average pore diameter. Using this prepreg makes it possible to provide a circuit board that is characterized, e.g., by low interstitial via connection resistance, excellent connection stability, and high durability.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: May 16, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Nakagiri, Takeshi Suzuki, Fumio Echigo