Patents by Inventor Fumio Echigo

Fumio Echigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7018705
    Abstract: It is an object of the present invention to provide a multilayer circuit board, and a method for manufacturing the same, in which a plurality of circuit boards are layered, wherein as regards at least one circuit board positioned on an outer side, a conductive substance is filled into holes passing through the circuit board in the thickness direction and cured, and the wiring layers of the plurality of circuit boards are electrically connected by the conductive substance that has been cured, wherein in the multilayer circuit board, the wiring layer positioned outside the conductive substance that has been cured projects outward from its surroundings. Thus, the conductive paste is sufficiently compressed during hot pressing to yield a stable electrical connection, and thermosetting resin can be filled in between the inner layer wiring pattern without leaving gaps.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: March 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Nakatani, Hideki Higashitani, Tadashi Nakamura, Fumio Echigo
  • Patent number: 6996902
    Abstract: A circuit board includes an electrical insulator layer formed of a reinforcer sheet with density distribution in its in-plane direction, an electrical conductor filled in a plurality of inner via holes provided in the electrical insulator layer in its thickness direction, and a wiring layer connected to the electrical conductor. The inner via holes provided in a high-density portion of the reinforcer sheet are formed to have a smaller cross-section than the inner via holes provided in a low-density portion of the reinforcer sheet. In this manner, it is possible to provide a circuit board that can achieve a high-density wiring and an inner via connection resistance with less variation, when a base material including a reinforcer sheet with density distribution in its in-plane direction such as a glass-epoxy base material is used for an insulator layer.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: February 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Toshihiro Nishii, Satoru Tomekawa, Fumio Echigo
  • Publication number: 20060008628
    Abstract: It is an object of the present invention to provide a multilayer circuit board, and a method for manufacturing the same, in which a plurality of circuit boards are layered, wherein as regards at least one circuit board positioned on an outer side, a conductive substance is filled into holes passing through the circuit board in the thickness direction and cured, and the wiring layers of the plurality of circuit boards are electrically connected by the conductive substance that has been cured, wherein in the multilayer circuit board, the wiring layer positioned outside the conductive substance that has been cured projects outward from its surroundings. Thus, the conductive paste is sufficiently compressed during hot pressing to yield a stable electrical connection, and thermosetting resin can be filled in between the inner layer wiring pattern without leaving gaps.
    Type: Application
    Filed: September 14, 2005
    Publication date: January 12, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yasuhiro Nakatani, Hideki Higashitani, Tadashi Nakamura, Fumio Echigo
  • Patent number: 6916706
    Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: July 12, 2005
    Assignee: Matsushita Electric Industrial Co, Ltd.
    Inventors: Fumio Echigo, Tadashi Nakamura, Daizo Andoh
  • Publication number: 20050139384
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Application
    Filed: February 18, 2005
    Publication date: June 30, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 6866892
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Publication number: 20050016764
    Abstract: There is provided a wiring substrate for intermediate connection comprising: (1) a wiring board having a plurality of wiring layers which are connected through a via hole conductor(s) with each other; and (2) a prepreg sheet having a via hole conductor(s) at a predetermined position(s) which sheet is disposed on at least one side of the wiring board.
    Type: Application
    Filed: July 23, 2004
    Publication date: January 27, 2005
    Inventors: Fumio Echigo, Kumiko Hirayama, Yoji Ueda, Yasuhiro Nakatani
  • Publication number: 20040231151
    Abstract: It is an object of the present invention to provide a multilayer circuit board, and a method for manufacturing the same, in which a plurality of circuit boards are layered, wherein as regards at least one circuit board positioned on an outer side, a conductive substance is filled into holes passing through the circuit board in the thickness direction and cured, and the wiring layers of the plurality of circuit boards are electrically connected by the conductive substance that has been cured, wherein in the multilayer circuit board, the wiring layer positioned outside the conductive substance that has been cured projects outward from its surroundings. Thus, the conductive paste is sufficiently compressed during hot pressing to yield a stable electrical connection, and thermosetting resin can be filled in between the inner layer wiring pattern without leaving gaps.
    Type: Application
    Filed: May 10, 2004
    Publication date: November 25, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yasuhiro Nakatani, Hideki Higashitani, Tadashi Nakamura, Fumio Echigo
  • Publication number: 20040214006
    Abstract: A member for a circuit board according to the present invention includes a prepreg and a mold release film that is provided on at lease one side of the prepreg. The mold release film contains or is coated with a heat absorbing substance having a heat absorbing property. A method of manufacturing a member for a circuit board according to the present invention includes allowing a mold release film to adhere to at least one side of a prepreg by heating and pressing. The mold release film contains or is coated with a heat absorbing substance having a heat absorbing property. In the method, the heating is performed at a temperature not lower than a softening point of the prepreg and not higher than an endothermic temperature of the heat absorbing substance.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 28, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kumiko Hirayama, Fumio Echigo, Izuru Nakai, Yoji Ueda
  • Publication number: 20040201367
    Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 14, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Tadashi Nakamura, Daizo Andoh
  • Patent number: 6799369
    Abstract: A printed circuit board of the present invention is formed of an electrical insulating base material with through holes that are formed in a thickness direction of the electrical insulating base material and are filled with an electrical conductor; the electrical insulating base material including a core layer formed by impregnating a holder with a resin and resin layers formed on both sides of the core layer; and wiring layers that are formed on both surfaces of the electrical insulating base material into a predetermined pattern and are electrically connected to each other by the electrical conductor. The wiring layer is embedded in at least one of the resin layers. The resin layers on the both sides have different thicknesses from each other, and a thinner layer out of the resin layers has a thickness equal to or smaller than a mean particle diameter of an electrically conductive filler contained in the electrical conductor.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shozo Ochi, Fumio Echigo, Yoji Ueda
  • Publication number: 20040142161
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 22, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 6756628
    Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Tadashi Nakamura, Daizo Andoh
  • Patent number: 6753483
    Abstract: The present invention provides a printed circuit board, which includes a dielectric substrate having via holes formed in the thickness direction, and a conductor including a conductive filler is filled in the via holes. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity. The present invention also provides a method of manufacturing such a printed circuit board.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Patent number: 6745464
    Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 8, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Hideki Higashitani, Daizo Andoh, Noritake Fukuda, Yasuhiro Nakatani, Tadashi Nakamura
  • Publication number: 20040089471
    Abstract: The present invention provides a printed circuit board, which includes a dielectric substrate having via holes formed in the thickness direction, and a conductor including a conductive filler is filled in the via holes. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity. The present invention also provides a method of manufacturing such a printed circuit board.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 13, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Patent number: 6734375
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Publication number: 20040080918
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Applicant: MUTSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6713688
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6694612
    Abstract: A mask film includes a base material, a parting layer and a non-parting portion placed on the base material. Accordingly, an optimum adhesion strength of the mask film and a prepreg sheet can be maintained, and peeling between the mask film and prepreg sheet can be prevented. Further, by preventing the fusing adhesion between the mask film and prepreg sheet due to heat generated when forming penetration holes, a circuit board having an excellent quality is obtained.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: February 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiaki Takenaka, Toshikazu Kondo, Kunio Kishimoto, Shinji Nakamura, Fumio Echigo