Patents by Inventor Fumio Harima
Fumio Harima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250080056Abstract: A semiconductor device includes: a first semiconductor element in which a plurality of transistors arranged in one direction are electrically connected in parallel, and a second semiconductor element provided in both end portions in the arrangement direction of the transistors, wherein the lower an ambient temperature is, the greater a current flowing through the second semiconductor element relatively increases.Type: ApplicationFiled: September 4, 2024Publication date: March 6, 2025Inventors: Masatoshi KAMITANI, Fumio HARIMA, Yoshiaki SUKEMORI, Yuuki NAKANO
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Patent number: 12231089Abstract: A control circuit is configured to control a Doherty amplifier including a carrier amplifier and a peak amplifier. The control circuit includes a resistor having a resistance value that is irreversibly adjustable. The resistor is configured to determine, based on the resistance value, a bias of the peak amplifier. The control circuit controls a Doherty amplifier.Type: GrantFiled: May 28, 2021Date of Patent: February 18, 2025Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Satoshi Tanaka, Fumio Harima, Satoshi Arayashiki
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Publication number: 20250022873Abstract: A bonding layer including a first metal region is disposed on at least a portion of an upper surface of a support substrate. An underlying layer including a sub-collector region that is made of a conductive semiconductor material and is electrically connected to the first metal region is disposed on the bonding layer. A first transistor including a collector layer electrically connected to the sub-collector region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer is disposed on the sub-collector region. On the sub-collector region, a collector electrode electrically connected to the sub-collector region is located outward of the first transistor to overlap the first metal region in plan view.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Applicant: Murata Manufacturing Co., Ltd.Inventors: Masayuki AOIKE, Shinnosuke TAKAHASHI, Masatoshi HASE, Fumio HARIMA
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Patent number: 12184245Abstract: A power amplifier circuit includes: a high pass filter that has one end into which a high frequency input signal is inputted; a first amplifier that amplifies the high frequency input signal outputted from the other end of the high pass filter and outputs a high frequency signal obtained through the first amplification; a second amplifier that amplifies the high frequency signal and outputs a high frequency output signal obtained through the second amplification; an automatic transformer that performs impedance matching between the first amplifier and the second amplifier; and an impedance circuit, one end of which is electrically connected with the other end of the high pass filter, the other end of which is electrically connected with an output terminal of a bias circuit outputting bias voltage or bias current to the first amplifier, and that outputs the high frequency input signal to the bias circuit.Type: GrantFiled: August 24, 2021Date of Patent: December 31, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Jun Enomoto, Yuri Honda, Satoshi Tanaka, Fumio Harima
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Patent number: 12160209Abstract: A power amplifier circuit includes a first amplifier circuit configured to amplify a first signal of a first frequency band and output a first amplified signal having a first power, a second amplifier circuit configured to amplify a second signal of the first frequency band or a second frequency band different from the first frequency band and output a second amplified signal having a second power different from the first power, and a first variable adjustment circuit disposed between the second amplifier circuit and a first circuit subsequent to the second amplifier circuit, the first variable adjustment circuit being configured to be capable of adjusting a first impedance of the first circuit seen from the second amplifier circuit.Type: GrantFiled: April 27, 2021Date of Patent: December 3, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Satoshi Arayashiki, Satoshi Tanaka, Fumio Harima, Satoshi Goto
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Patent number: 11996809Abstract: There is provided a power amplifier circuit with improved operation speed of the protection function against overcurrent or overvoltage. The power amplifier circuit includes an amplifier configured to amplify a radio frequency signal and output the radio frequency signal, a bias current supply circuit configured to supply a bias current to the amplifier, a detection circuit configured to detect whether the current or voltage of the amplifier is equal to or greater than a predetermined threshold; and a draw circuit configured to, when the detection circuit detects that the current or voltage is equal to or greater than the predetermined threshold, draw at least a part of the bias current supplied to the amplifier.Type: GrantFiled: April 14, 2021Date of Patent: May 28, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Fuminori Morisawa, Kazuhiko Ishimoto, Fumio Harima
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Patent number: 11901867Abstract: A differential amplifier circuit includes a first and second amplifiers that output a differential signal in a radio-frequency band, a first inductor having a first end connected to an output end of the first amplifier, a second inductor having a first end connected to an output end of the second amplifier, a choke inductor connected to second ends of the first and second inductors, a first and second capacitors, and a switch that connects the second capacitor in parallel to the first capacitor or terminates a parallel connection of the first and second capacitors. A resonant circuit formed by connecting the first or second inductor in series with the first capacitor has a different resonant frequency from a resonant circuit formed by connecting the first or second inductor in series with the parallel-connected first and second capacitors. These resonant frequencies correspond to second harmonic frequencies of the differential signal.Type: GrantFiled: June 17, 2021Date of Patent: February 13, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Jun Enomoto, Fumio Harima, Satoshi Tanaka
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Patent number: 11876032Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.Type: GrantFiled: October 18, 2021Date of Patent: January 16, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Shinnosuke Takahashi, Masayuki Aoike, Masatoshi Hase, Fumio Harima
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Publication number: 20230223969Abstract: A radio frequency module includes a module substrate including major surfaces that face each other; a first base part that is at least partially comprised of a first semiconductor material and in which an electronic circuit is formed; a second base part that is at least partially comprised of a second semiconductor material having a thermal conductivity lower than the thermal conductivity of the first semiconductor material and in which an amplifier circuit is formed; and an external connection terminal disposed on or over the major surface. The first base part and the second base part are disposed on or over the major surface out of the major surfaces; and the second base part is disposed between the module substrate and the first base part, is joined to the first base part, and is connected to the major surface via an electrode.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Inventors: Yukiya YAMAGUCHI, Fumio HARIMA, Takanori UEJIMA, Yuji TAKEMATSU, Shunji YOSHIMI, Satoshi ARAYASHIKI, Mitsunori SAMATA, Satoshi GOTO, Masayuki AOIKE
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Patent number: 11677367Abstract: A power amplifier circuit includes a power splitter, a first amplifier configured to output a first amplified signal from a first output terminal, and a second amplifier configured to output a second amplified signal from a second output terminal. The power amplifier circuit further includes a first termination circuit connected between the first output terminal and the second output terminal, a first transmission line, a second transmission line, a second termination circuit connected between another end of the first transmission line and another end of the second transmission line, and a power combiner.Type: GrantFiled: October 28, 2021Date of Patent: June 13, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Satoshi Goto, Fumio Harima
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Patent number: 11677363Abstract: A power amplifier circuit includes a first transistor configured to receive a first signal at a base, amplify the first signal, and output a second signal from a collector; and a bias circuit configured to supply a bias current to the base of the first transistor. The bias circuit includes a second transistor configured to supply a bias current to the base of the first transistor, a third transistor including a base connected to a base of the second transistor and a collector connected to a collector of the second transistor, and a fourth transistor including a base connected to an emitter of the third transistor and a collector connected to an emitter of the second transistor and configured to draw at least part of the bias current.Type: GrantFiled: May 26, 2020Date of Patent: June 13, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Fumio Harima, Mitsuhiro Toya
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Patent number: 11616479Abstract: A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.Type: GrantFiled: April 3, 2020Date of Patent: March 28, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Toshikazu Terashima, Fumio Harima, Makoto Itou, Satoshi Tanaka, Kazuo Watanabe, Satoshi Arayashiki, Chikara Yoshida
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Patent number: 11601102Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.Type: GrantFiled: February 5, 2021Date of Patent: March 7, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hiroaki Tokuya, Hideyuki Sato, Fumio Harima, Kenichi Shimamoto, Satoshi Tanaka, Takayuki Kawano, Ryoki Shikishima, Atsushi Kurokawa
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Patent number: 11569786Abstract: A power amplifier circuit includes an amplifier transistor having a base, a collector, a bias circuit, and a first resistance element connected between the base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied, and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied, and an emitter connected to the emitter of the first transistor, a signal supply circuit disposed between the base of the amplifier transistor and the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.Type: GrantFiled: March 10, 2021Date of Patent: January 31, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Fumio Harima, Satoshi Tanaka
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Patent number: 11469187Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.Type: GrantFiled: July 30, 2020Date of Patent: October 11, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Tokuya, Masahiro Shibata, Akihiko Ozaki, Satoshi Goto, Fumio Harima, Atsushi Kurokawa
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Patent number: 11463060Abstract: The present disclosure provides a power amplifier circuit capable of suppressing the occurrence of noises while enabling control of an output power level. The power amplifier circuit includes a first transistor that amplifies a first signal; a bias circuit that supplies a bias current or voltage based on a control signal to the first transistor; a second transistor to which a control current based on the control signal is supplied, which has an emitter or a source thereof connected to a collector or a drain of the first transistor, and from which a second signal obtained by amplifying the first signal is output; and a first feedback circuit provided between the collector or the drain of the second transistor and the base or the gate of the second transistor.Type: GrantFiled: September 30, 2020Date of Patent: October 4, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Fumio Harima, Yoshiki Kogushi, Shota Ishihara, Fuminori Morisawa
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Patent number: 11444582Abstract: A power amplifier circuit includes an amplifier transistor, a bias circuit that supplies a bias current or voltage to the amplifier transistor, and a resistance element connected between a base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied and an emitter connected to the emitter of the first transistor, a signal supply circuit that supplies an input signal to the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.Type: GrantFiled: January 27, 2021Date of Patent: September 13, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Kenji Mukai, Fumio Harima
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Patent number: 11444585Abstract: A power amplifier includes power amplification circuits in a plurality of stages including a first stage and a second stage, each power amplification circuit including a transistor. The power amplification circuit in the first stage includes a first impedance circuit between an emitter of the transistor and a reference potential. The first impedance circuit has an impedance that does not vary with frequency or an impedance that varies with frequency. The power amplification circuit in the second stage includes a second impedance circuit between an emitter of the transistor and a reference potential. The second impedance circuit has an impedance that does not vary with frequency or an impedance that varies with frequency.Type: GrantFiled: May 9, 2019Date of Patent: September 13, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuri Honda, Fumio Harima, Kenji Mukai
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Publication number: 20220157748Abstract: A mounting substrate has one main surface (a first main surface). An electronic component has a first face, a second face, and a side face, and is provided on the one main surface of the mounting substrate. A solder bump is disposed between the mounting substrate and the electronic component, and electrically connects the mounting substrate and the electronic component. A resin layer is provided on the one main surface of the mounting substrate to cover the electronic component. The first face is a face of the electronic component at a side opposite to the mounting substrate. The side face of the electronic component is in contact with the resin layer. A space is provided between at least a part of the first face and the resin layer in a thickness direction of the mounting substrate.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: Mayuka ONO, Motoji TSUDA, Fumio HARIMA, Koshi HIMEDA, Hiroaki TOKUYA
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Publication number: 20220122901Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Applicant: Murata Manufacturing Co., Ltd.Inventors: Shinnosuke TAKAHASHI, Masayuki AOIKE, Masatoshi HASE, Fumio HARIMA