Abstract: An information processing apparatus includes a hinge mechanism for rotating an integral type hand writing input/display device and a keyboard from a position, in which the display surface of the integral type hand writing input/display device and the surface of the keyboard face each other, to a position of a desired opening angle. The input/display device is provided on a top portion of a processing apparatus body, is constituted by integrally superposing a tablet device for coordinate input on a display surface of a display device, and inputs coordinate data representing a location indicated voluntarily on the tablet device. The hinge mechanism can retain the desired opening angle.

Abstract: An apparatus for generating a high-quality pattern comprises a code pattern memory for storing a plurality of first winding number (WN) codes, a projection section responsive to an input projection start command, for projecting at least one size change contour line of input size changed contour line data for defining an area of the pattern in the code pattern memory while updating the first WN codes with second WN codes determined in accordance with a drawing direction of the size changed contour line and a filling direction in units of dots representing the size changed contour line, and for generating a projection end response upon completion of projection of the size changed contour line, a filling section responsive to an input filling start command, for filling the area in accordance with the first WN codes read out from the code pattern memory obtain the pattern, and a controller for outputting the projection start command to the projection section in response to an input pattern generation instruction

Abstract: An outline font formation which when a character is in a regularly-used size, forms a character pattern by approximation with short line segments using an outline font of a first representing mode. When a large character is designated, and the magnification thereof exceeds the limit value, and the character pattern is formed by using an outline of the second representing mode which is able to avoid the deterioration of the quality of the character pattern represented by the first representing mode at the same magnification.

Abstract: When a variable length code requires two cycles in decoding, portions of code bit strings serving as objects to be decoded in first and second cycles of the variable length code are caused to overlap each other. In the first cycle, a non-overlapping portion is determined as a decoded portion. A length of a code bit string actually decoded in the first cycle is determined as a length of the code bit string serving as the object to be decoded in the first cycle excluding the length of the overlapping portion so as to determine a start position of the code bit string serving as the object to be decoded in the second cycle.

Abstract: A value of a parameter t corresponding to the adjacent next plot point on a bit map memory in an x or y direction is calculated, one of the x or y coordinate values of a current plot point is changed by 1 to calculate a coordinate in the same direction of the next plot point, and the other coordinate of the next plot point is calculated on the basis of an approximated parameter t and cubic curve, thereby plotting the next plot point on the bit map memory.

Abstract: A binary data compression and exansion processing apparatus of this invention has an input data holding section for holding input code data. In an address section, bit data having a predetermined length is selected from code data held in the holding section in accordance with an instruction from an addition section, and address data for a decode section is generated from instruction data from a control section and the selected data. The decode section generates data associated with the run length in response to the generated address data, and outputs data indicating the length of the decoded code data portion. The addition section adds the data indicating the length to the previous instruction, and outputs sum data as the next instruction. When the sum data becomes equal to an input bit width, the control section outputs an instruction to the input data holding section so as to input the next code data.

Abstract: According to a binary data compression and expansion processing apparatus of this invention, a reference line data storage section for storing reference line data is separately provided from an image data memory. Binary data input through an input data bus is subjected to compression and expansion processing by a compression and expansion processing section in accordance with reference line data read out from the reference line data storage section, and the processed result is output to an external device through an output data bus. The compression and expansion processing section comprises a decoding processing section, for generating run length data corresponding to input encoded data in expansion processing, and a generation processing section, for generating image data in expansion processing.

Abstract: According to a binary data expansion processing apparatus of this invention, unicolor image data is generated in a generation section in accordance with data associated with a run length and a color instruction for designating the color of image data to be generated. Unicolor image data exceeding the generated set is combined following the already-generated image data portion in accordance with a point a0, thus generating image data for a byte block of interest. At the same time, a color change point on a reference line corresponding to the byte block of interest is detected by a b1 detector. It is checked from the detected color change point if the combined image data exceeds a byte length. If the combined image data exceeds the byte length, the combined image data for one byte of the combined image data is output to an external device.

Abstract: In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address.

Abstract: The invention provides a device and method for data processing.

Abstract: A data processing system having an address conversion system for translating a virtual address into a real address, including a main memory for storing instructions and data and a second memory for storing an address conversion table including a plurality of entries, each of which consists of a plurality of control bits and a portion of a real address. A central processing unit executes the instruction stored in the main memory according to a microprogram. An addressing means addresses the second memory by a continuous portion, which includes the effective upper most bit of the virtual address for the address conversion and for updating of the conversion table. The main memory need not store the conversion table.

Abstract: In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address.

Abstract: In a picture data record/playback system, picture data and code data is recorded onto two fields of a record, which fields constitute a single picture in an optical disk unit. When the picture data is subjected to a cyclic redundancy check and an error is detected, the first error correction, for which the bit error rate of error correction is not too high, is applied to the picture data. The code data is doubly recorded onto the optical disk unit. Both items of recorded data are compared to each other. When such items are not coincident with each other, the CRC check is applied to both items of data which are doubly recorded. The valid code data is then selected. Further, when an error is detected, a CPU executes a second error correction, under program control, of which the bit error rate for error correction is not too low.

Abstract: An information processing system using a virtual addressing for paging, including a main memory, a memory controller, a central processing unit for processing information and accessing the memory controller with a virtual address, an input/output controller for interfacing input/output devices with the memory controller and the central processing unit, a common bus for interconnecting the memory controller, the central processing unit and the input/output controller with each other. The memory controller includes a translator for translating the virtual address into a real address, whereby the virtual address is available for addressing the main memory after being translated into the real address.

Abstract: A data processing system including a central processing unit (CPU) having an operating system to process information, and a main memory coupled to the CPU to store information, wherein the CPU accesses the main memory by means of an actual address after translating an associative address into the actual address by means of the operating system. To that end, the CPU includes a dynamic address translator having a page table addressed by the associative address and outputting a portion of the actual address when being addressed by the associative address. A remaining portion of the actual address is derived from the associative address itself.

Abstract: Disclosed is an information processor provided with a main memory device capable of simultaneously reading or writing 2N bit data. 2N bit data read out from the main memory device is applied to a selector through a memory bus of 2N-bit construction. The selector devides the data comprising 2N bits in two N-bit units and then outputs that data into a scratch pad memory device constituted by N bits X M addresses. The data written in the scratch pad memory device in N bit units is processed by a central processing unit of N-bit architecture. For accessing the operand, the information processor accesses the main memory in N-bit units.

Abstract: In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits.

Abstract: A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store.

Abstract: An address conversion system comprises an improved associative memory circuit for providing a real address corresponding to an applied virtual address with reference to the correspondence between virtual and real addresses stored in a main memory. The associative memory includes first and second memories for storing a part of the correspondence between virtual and real addresses. The second memory is essentially a set associative memory but is not connected with address comparators directly. The first memory is higher in speed but smaller in capacity than the second memory. When the first memory stores the correspondence between the virtual and real address corresponding to the applied virtual address, the real address corresponding to the applied virtual address is immediately delivered.

Abstract: An information processing system of the microprogram control type having a control storage is provided with an exclusive memory unit for storing only the address information of a microprogram stored in the control storage and an exclusive control circuit for reading a specific microprogram out of the control storage by the address information from the exclusive memory unit and executing the program read out. The exclusive control circuit operates when the information processing unit is an idle state to execute successively the micro-steps of the specified microprogram read out in accordance with the address information in the exclusive memory unit, thereby to verify the information processing unit.