Abstract: A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched into an active region of the substrate forming a plurality of mesas. A preselected area in the active region is oxidized and then etched using a dry process oxide etch to remove the oxide in the bottoms of the trenches. A protective shield is formed over a region at a border between the active region and the termination region. The protective shield is partially removed from over the preselected area. Dopants are implanted at an angle into mesas in the preselected area. The plurality of trenches are with an insulating material, the top surface of the structure is planarized and a superjunction device is formed on the structure.

Abstract: A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.

Abstract: A method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell includes the steps of opening a gate trench in a semiconductor substrate and implanting ions of a first conductivity type same as a conductivity type of a source region with at least two levels of implanting energies to form a column of drain-to-source resistance reduction regions below the gate trench. The method further includes steps of forming a gate in the gate trench and forming body and source regions in the substrate surrounding the gate trench. Then the MOSFET cell is covered with an insulation layer and proceeds with applying a contact mask for opening a source-body contact trench with sidewalls substantially perpendicular to a top surface of the insulation layer into the source and body regions.

Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.

Abstract: A vertical semiconductor power device includes a plurality of semiconductor power cells connected to a bottom electric terminal disposed on a bottom surface of a semiconductor substrate and at least a top electrical terminal disposed on a top surface of the substrate and connected to the semiconductor power cells. The top electrical terminal further includes a solderable front metal for soldering to a conductor for providing an electric connection therefrom. In an exemplary embodiment, the conductor soldering to the solderable front metal includes a conductor of a high-heat-conductivity metal plate. In another exemplary embodiment, the conductor soldering to the solderable front metal includes a copper plate. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Au front metal. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Ag front metal.

Abstract: A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.

Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.

Abstract: A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

Abstract: A hybrid semiconductor power device that includes a plurality of closed power transistor cells each surrounded by a first and second trenched gates constituting substantially a closed cell and a plurality of stripe cells comprising two substantially parallel trenched gates constituting substantially an elongated stripe cell wherein the closed cells and stripe cells constituting neighboring cells sharing trenched gates disposed thereinbetween as common boundary trenched gates. The closed MOSFET cell further includes a source contact disposed substantially at a center portion of the closed cell wherein the trenched gates are maintained a critical distance (CD) away from the source contact.

Abstract: A method for operating a semiconductor power device by in a forward conducting mode instead of an avalanche mode during a voltage fly-back during an inductive switch operation for absorbing a transient energy with less stress. The method includes a step of clamping the semiconductor power device with a Zener diode connected between a gate metal and a drain metal of the semiconductor power device to function as a gate-drain (GD) clamp diode with the GD clamp diode having an avalanche voltage lower than a source/drain avalanche voltage of the semiconductor power device whereby as the voltage fly-back inducing a drain voltage increase rapidly reaching the avalanche voltage of the GD clamp diode for generating the forward conducting mode.

Abstract: A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further includes a first epitaxial layer above heavily doped substrate and beyond the trench bottom and a second epitaxial layer above said first epitaxial layer wherein a resistivity N1 of said first epitaxial layer is greater than a resistivity N2 of said second epitaxial layer represented by a functional relationship of N1>N2. In an exemplary embodiment, each of the trenched gates include an upper gate portion and lower gate portion formed with single polysilicon deposition processes wherein the lower gate portion is surrounded with a lower gate insulation layer having a greater thickness than an upper gate insulation layer surrounding the upper gate portion.

Abstract: A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.

Abstract: A semiconductor power device includes a plurality of trenched gates. The trenched gates include a thin dielectric layer padded sidewalls of the trenched gate and a tub-shaped thick dielectric layer below a bottom of the trenched gates having a width narrower than the trenched gate. In an exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further includes a local deposition of silicon oxide (LOCOS) filling in a tub-shaped trench having a narrower width than the trenched gate. In another exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further comprising a high density plasma (HDP) chemical vapor deposition (CVD) silicon oxide filled in a tub-shaped trench having a narrower width than the trenched gate.

Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.

Abstract: A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin

Abstract: A vertical semiconductor power device includes a plurality of semiconductor power cells having a drain disposed at a bottom of a semiconductor substrate. Each of the cells includes a gate surrounded by a body region encompassing a source region. The body region further includes multiple body-dopant implanted regions having a non-Gaussian distribution dopant profile for reducing a width of a transition region transitioning between the multiple body-dopant implanted regions and an epitaxial region underneath having a different conductivity type from the multiple body-dopant implanted regions.

Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.

Abstract: A vertical semiconductor power device includes a plurality of semiconductor power cells connected to a bottom electric terminal disposed on a bottom surface of a semiconductor substrate and at least a top electrical terminal disposed on a top surface of the substrate and connected to the semiconductor power cells. The top electrical terminal further includes a solderable front metal for soldering to a conductor for providing an electric connection therefrom. In an exemplary embodiment, the conductor soldering to the solderable front metal includes a conductor of a high-heat-conductivity metal plate. In another exemplary embodiment, the conductor soldering to the solderable front metal includes a copper plate. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Au front metal. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Ag front metal.