Abstract: A system for converting DC power (22) into an RF electromagnetic field in a processing chamber, the system being composed of: a coil (16) constructed to surround the processing chamber; and an RF power generator (20) including a free-running oscillator (26) having a DC power input and an RF power output, the power output connected to a load impedance which includes the coil for supplying RF current to the coil at a frequency which is dependent on the load impedance.

Abstract: An apparatus for testing an integrated circuit, the apparatus including a sequence control logic unit having an output channel connectable to a device under test, and a memory to store at least two types of data sets, each data set being used by the sequence control logic unit to determine a test pattern to output on the output channel.

Abstract: A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

Abstract: A medical monitoring system includes a central station adapted to receive vital signs data concerning a plurality of patients, and one or more transmitter/receivers associated with the central station. At least one patient monitor is configured to monitor a particular one of the plurality of patients by collecting vital signs data from the particular patient, and configured to establish communications with the central station and communicate the collected vital signs data to the central station via the one or more transmitter/receivers. The at least one patient monitor is operable by a user to identify the particular patient from the plurality of patients, and to inform the central station of the identity of the particular patient. The central station is configured to associate the vital signs data received from the at least one patient monitor with the particular patient. The system, transmitter/receivers and at least one patient monitor may be wireless or wired.

Abstract: The present invention discloses methods for preparing a processed peanut product containing high levels of peanut hearts material, with the peanut heart material being substantially stripped of bitter taste so as to provide debittered peanut hearts of comparable taste to actual peanuts or as being flavorless without adversely affecting the taste of a foodstuff end product. The processed product includes whole or fragmented peanut hearts and peanut heart powder processed using alkaline wash, neutralization, and drying for inactivating enzymes and removing bitter flavoring components. The peanut heart materials are debittered by adjusting the pH to about 8 to about 12 with an alkali material (e.g., sodium hydroxide) to solubilize the protein content and release the bitter flavor compounds making it possible to separate such compounds by ultrafiltration. The alkali treated peanut heart material is neutralized with an acidic aqueous solution.

Abstract: An apparatus compares propagation delay of electronic by using flip-flops or similar storage elements. The apparatus includes a strobe source having an output line coupled to a control terminal of a pattern source and an input terminal of a variable clock delay. The strobe source triggers the pattern source to output signal a sequence of signals to an input terminal of an element or device under test (DUT). The DUT propagates the signals to a flip-flop. The output signal of the flip-flop is captured after a delay. The propagation delay of the DUT is determined by coinciding the clock signal edge with the data signal edge to the flip-flop so that the flip-flop enters the ambiguity region. Once the delay settings that define the ambiguity region under the same delay are determined for various DUTs, they are compared to determine which DUT has the least propagation delay.

Abstract: The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.

Abstract: A rack for holding a bicycle by either its front or back wheel in an upright position on a floor. The rack includes a bracket which is adapted to be fitted on an elongate support frame. A rotatable lower brace extends outwardly from the bracket and includes spaced-apart arms which terminate in a downwardly extending lip. An upper brace extends generally upwardly from the bracket and includes spaced-apart arms. A bicycle is held on the rack by rolling the bicycle wheel directly into the lip of the lower brace and into and between the arms of the upper and lower braces respectively. A plurality of racks can be slidingly fitted onto a single support frame for holding a plurality of bicycles in spaced-apart relationship.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: A wireless medical telemetry system includes at least one wireless patient monitor configured to collect patient vital signs data, and at least one central station adapted to establish communications with the at least one patient monitor via a wireless transceiver, and to receive the patient vital signs data from the at least one patient monitor. The at least one patient monitor is operable by a user to transmit an end-communications signal to the at least one central station, and the at least one central station is configured to terminate the communications with the at least one patient monitor in response to the end-communications signal.

Abstract: A wireless patient monitor is adapted to communicate with any one of plural medical telemetry networks, each having one or more central stations, where each network is configured to communicate via wireless communications using one of multiple different communications settings. The monitor includes one or more sensor inputs for receiving vital signs data from a patient, a wireless transceiver; and a controller coupled to receive the vital signs data via the one or more sensor inputs and to communicate with a network via the transceiver. The monitor also includes a display device and is controllable by the controller to automatically display a notification to a user of the monitor upon establishing communications with the at least one central station. There is also a method of monitoring a patient and a wireless medical telemetry system.

Abstract: A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test..

Abstract: A test system formatter may include a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode corresponding to a different combination of drive signals or drive timing markers or both, and a programmable response circuit configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals. The formatter may also include multiple drive channels and/or multiple response channels, each channel being formed, e.g., of an event logic interface and a corresponding linear delay element. The drive channels provide signals to the drive circuit to be used to generate drive signals or drive timing markers or both. The response channels receive from one or more pin-electronics comparators response signals used to generate fail outputs. The programmable drive and response circuits are configurable to route signals through multiple channels in parallel.

Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

Abstract: A time-to-digital converter records the arrival times of successive signals—which are separated from one another by more than one period of a reference clock signal—by recording the number of nodes disposed within a plurality of fine delay paths—each coupled to a different one of a plurality of coarse delay stages in a first coarse delay path—through which the signals propagate. The delay across each fine delay path is substantially the same as the delay across a coarse delay stage in the coarse delay path. A phase detector maintains the clock signal and its delayed replica in phase by adjusting the delay through each of the coarse delay stages in a second coarse delay path. The time delay between the clock signal and its delayed replica is equal to one period of the clock signal.

Abstract: The present invention relates to fluorescent cobalamins and uses of these compounds. More particularly, this invention relates to fluorescent cobalamins that comprise a fluorescent, phosphorescent, luminescent or light-producing compound covalently linked to cobalamin. These fluorescent cobalamins can be used to as diagnostic and prognostic markers (a) to distinguish cancer cells and tissues from healthy cells and tissues, including identifying lymph nodes containing cancer cells, and (b) to determine if an individual will respond positively to chemotherapy using cobalamin-therapeutic bioconjugates.

Abstract: Testing an integrated circuit (IC) device, for example, an IC that includes an embedded memory, may involve specifying one or more test parameters including at least one of a pipeline depth data (e.g., latency delay information) and a data width data (e.g. corresponding to a data width of an embedded memory), generating a test sequence by associating test parameters with a test pattern, and applying the generated test sequence to the integrated circuit device. A test system for testing ICs having embedded memories may include multiple test patterns and multiple data structures, each data structure defining one or more test parameters including at least one of a pipeline depth and a data width, an algorithmic pattern generator, and software for controlling the algorithmic pattern generator to generate a test sequence by associating a specified data structure with a specified test pattern.

Abstract: A folded gusseted plastic bag has a first side gusset formed by first, second, and third longitudinal folds, a second side gusset formed by fourth, fifth, and sixth longitudinal folds, a seventh longitudinal fold being on a side of the bag containing the first, second, and third folds and forming a first folded bag flap, and an eighth longitudinal fold which is on a side of the bag containing the fourth, fifth, and sixth folds, the eighth fold forming a second folded bag flap. The folded gusseted bag also is folded into a total of at least eight contiguous plies. A roll of the folded, gusseted bags includes a continuous web of the folded, flattened bags joined along perforated severance lines. Preferably the perforated severance lines further comprise a centrally-located slit.

Abstract: Systems and methods for enabling automobile dealers to select a loan for a prospective customer are disclosed. The selection is made from an extensive database of loans comprising loan packages from a plurality of financial institutions and other sources. The selection is determined according to a series of complex calculations designed to meet customer criteria, maximize dealer profit, and minimize waiting-time.