Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.snyc) that controls a line scan rate, and a vertical synchronizing signal (V.sub.snyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.sync) that controls a line scan rate, and a vertical synchronizing signal (V.sub.sync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: A method and device for teaching a given language to one or more users in an entertaining manner is provided utilizing a media series for teaching a given language to one or more users, particularly young children. The media series contains the given language as well as language other than the given language and is made up of series lessons which sequentially contain an increasing percentage of the given language. A user is progressively exposed to the media series by exposing the user to the series lessons in sequential fashion beginning with a first series lesson containing a lowest percentage of the given language and ending with a last series lesson containing a highest percentage of the given language. The given language to be learned is utilized and presented strategically such that the meaning of the given language can be readily and intuitively understood and wherein no supervision is necessary.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: An array of panels foldably connected such that the array may be collapsed into a single stack of panels, and a method of manufacturing such an array. The array has at least three rows of panels, where the first and second rows have at least two panels and the third row has at least one panel. The panels in each row are foldably connected so that each row of panels may be collapsed into a single stack of panels. Each row of panels is connected to the row of panels below it so that the individual stacked rows may be further collapsed onto each other to form a single stack of panels. With this folding scheme, the array may have more than two panels in each row and may have more than three rows of panels. The panels define connecting pin channels that, when the panels are unfolded, are co-axially aligned with connecting pin channels of adjacent panels. Connecting pins are inserted into the co-axially aligned connecting pin channels to hold panels in a specific orientation with respect to each other.

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit.

Abstract: Driver circuits are provided which also serve as termination and clamp in an IC tester. When it is to drive a port of a device under test (DUT) between two predetermined voltage levels, the driver's I/O terminal is switched between two predetermined voltage levels with an output impedance that matches the transmission line between the driver circuit and the DUT. When the DUT's port is supplying an output signal, the driver circuit can be programmed to provide one of two types of termination. If the DUT's port is specified as capable of driving the load, the transmission line between the driver circuit and the DUT is terminated by switching the driver circuit's I/O terminal to a predetermined voltage level with an impedance of Z.sub.0. If the DUT's port is not specified as being capable of driving such a termination load, the driver circuit functions like a Z-clamp circuit.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: There is disclosed herein a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew. The invention is particularly useful in field programmable gate arrays where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable. Clock skew is eliminated by generating differential clock signals at each of four corners of the array from master differential clock signal delivered simultaneously to each of the four corners. The differential clock signals generated at each corner have ramps the rise time of which slightly exceeds the propagation delay of a clock signal traversing the array.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: The scanning force microscope includes integrated optics for viewing the optical lever arm, probe and sample to be examined. The scanning force microscope includes an improved mount for the probe, which is magnetically secured to the body of the scanning force microscope, to improve ease of handling and mounting the probe assembly. In one preferred embodiment the scanning force microscope, also includes a base portion with a fluid cell for receiving a sample in a sealed gas or liquid environment.

Abstract: An infant's toy that is both visually and audibly attractive to an infant and which has a soft inner layer of any desired shape formed of a foam rubber material, a pliable sound-generating layer including a sound-generating means covering at least a portion of the soft inner layer for causing a noise to attract the infant when handled by the infant, and a cloth outer layer entirely covering the soft inner layer and the pliable layer including the sound-generating means to form a unitary infant's toy. The outer layer may have brightly colored designs thereon to visually attract the infant.

Abstract: A system for fusion bonding several attachments to a relatively large and bulky thermoplastic article employs means for fixedly securing the article, and a movable fixture selectively positionable relative to the thermoplastic article. The fixture includes a base plate held stationary during bonding operations, a gripping device supporting the thermoplastic article and longitudinally reciprocable relative to the base plate, and a pair of arms supporting a platen or other heating tool, also longitudinally reciprocable relative to the base plate. The tool supporting arms further can be pivoted to move the heating tool between an aligned position between the thermoplastic attachment and fixed thermoplastic article, and a remote, withdrawn position, to allow longitudinal movement of the attachment into engagement with the thermoplastic article, following use of the heating tool to simultaneously fuse selected surface portions of the thermoplastic article and attachment.

Abstract: A carousal apparatus is set forth wherein a ground supported base integrally secures a first post extending upwardly thereof with a second post telescopingly secured thereover. The second post telescopingly receives at an upper end thereof a third post rotatably mounted therein with a cap member overlying the second post to sandwich the second post between the third post and cap member to rotatably mount the third post therein. A flange plate is orthogonally secured to the third post receiving four downwardly extending support rods. The support rods are positioned through the flange plate and welded thereto in a quadrangular orthogonally oriented relationship to enhance integrity of the organization. A non-skid support plate is secured to the support rods where individuals may stand upon the support plate and simultaneously grasp the support rods during a spinning event.

Abstract: A contact heating platen assembly includes an upright central standard, a plurality of inclined linking members pivotally mounted to the standard, and to a pair of opposed platen carriers on opposite sides of the standard, each traversing an arcuate path relative to the standard. Each of the carriers supports a heating platen and an electrical heating element for heating the platen. The carriers are spring biased into a collapsed position against the standard, but movable to an extended position relatively remote from the standard. To complete a fusion bond, a pair of workpieces are positioned on opposite sides of the platen assembly, each with a fusible surface portion positioned to be engaged by one of the platens when the assembly is extended. The assembly is extended whereby the heated platens engage the fusible surface portions. The platens are maintained against the surface portions until they are fused, then allowed to retract or collapse under the spring force.

Abstract: A dynamic frame length slotted ALOHA communication system has a central station which monitors the traffic congestion and determines the optimum frame length. This is transmitted to the sub-stations in the form of a service information message when there is to be a change in the frame length but not, as is conventional, at the beginning of each frame. The amount of time available for the useful transmission of communication messages is thus optimized.

Abstract: In a dynamic frame length slotted ALOHA system the synchronizing signals are transmitted by a base station at different frequencies (each having a period equivalent to a multiple of the time slot period). The different frequencies denote different frame lengths and the central stations detect these frequencies and select a frame length accordingly.

Abstract: A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators.