Patents by Inventor Gabriele Barlocchi

Gabriele Barlocchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7678600
    Abstract: A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 16, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Francesco Villa, Pietro Corona, Chantal Combi, Lorenzo Baldo, Gabriele Barlocchi
  • Patent number: 7635454
    Abstract: The microreactor is formed by a sandwich including a first body, an intermediate sealing layer and a second body. A buried channel extends in the first body and communicates with the surface of the first body through a first and a second apertures. A first and a second reservoirs are formed in the second body and are at least partially aligned with the first and second apertures. The sealing layer separates the first aperture from the first reservoir and the second aperture from the second reservoir, thereby avoiding contamination of liquids contained in the buried channel from the outside and from any adjacent buried channels. The sealing layer is perforated during use of the device, but a resilient plug can be used to reseal the device.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: December 22, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ubaldo Mastromatteo, Flavio Francesco Villa, Gabriele Barlocchi
  • Patent number: 7452713
    Abstract: A process for manufacturing a microfluidic device, including the steps of: forming at least one channel in a semiconductor material body; forming a dielectric diaphragm above the channel, for closing the channel; and forming heating elements for providing thermal energy inside the channel. The heating elements are formed directly on said dielectric diaphragm.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: November 18, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Pietro Corona, Ubaldo Mastromatteo, Flavio Villa
  • Publication number: 20080261345
    Abstract: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of the walls and to form a closed cavity underneath the suspended membrane; and structures are formed for transducing the deflection of the suspended membrane into electrical signals.
    Type: Application
    Filed: June 27, 2008
    Publication date: October 23, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Flavio Francesco Villa, Gabriele Barlocchi, Pietro Corona, Benedetto Vigna, Lorenzo Baldo
  • Publication number: 20080224242
    Abstract: A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Flavio Franceso Villa, Pietro Corona, Chantal Combi, Lorenzo Baldo, Gabriele Barlocchi
  • Patent number: 7348257
    Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: March 25, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Flavio Francesco Villa
  • Publication number: 20080036030
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Application
    Filed: September 28, 2007
    Publication date: February 14, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20080029817
    Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.
    Type: Application
    Filed: July 17, 2007
    Publication date: February 7, 2008
    Inventors: Gabriele Barlocchi, Pietro Corona, Flavio Francesco Villa
  • Patent number: 7294536
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: November 13, 2007
    Assignee: STMicroelectronics S.R.L.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20070252224
    Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 1, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Ubaldo Mastromatteo, Flavio Villa
  • Patent number: 7230315
    Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 12, 2007
    Assignee: STMicroelectronics S.r.L.
    Inventors: Gabriele Barlocchi, Ubaldo Mastromatteo, Flavio Francesco Villa
  • Publication number: 20070126071
    Abstract: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.
    Type: Application
    Filed: September 27, 2006
    Publication date: June 7, 2007
    Inventors: Pietro Corona, Flavio Villa, Gabriele Barlocchi
  • Publication number: 20070057355
    Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.
    Type: Application
    Filed: July 12, 2006
    Publication date: March 15, 2007
    Inventors: Gabriele Barlocchi, Pietro Corona, Dino Faralli, Flavio Villa
  • Publication number: 20070042558
    Abstract: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.
    Type: Application
    Filed: June 6, 2006
    Publication date: February 22, 2007
    Inventors: Flavio Villa, Pietro Corona, Gabriele Barlocchi
  • Publication number: 20060260408
    Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 23, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Pietro Corona, Gabriele Barlocchi, Lorenzo Baldo
  • Patent number: 7071073
    Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: July 4, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20060063352
    Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 23, 2006
    Applicant: STMicroelectronics S.r.I
    Inventors: Gabriele Barlocchi, Flavio Villa
  • Patent number: 7009154
    Abstract: The microreactor is completely integrated and is formed by a semiconductor body having a surface and housing at least one buried channel accessible from the surface of the semiconductor body through two trenches. A heating element extends above the surface over the channel and a resist region extends above the heating element and defines an inlet reservoir and an outlet reservoir. The reservoirs are connected to the trenches and have, in cross-section, a larger area than the trenches. The outlet reservoir has a larger area than the inlet reservoir. A sensing electrode extends above the surface and inside the outlet reservoir.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: March 7, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Ubaldo Mastromatteo, Gabriele Barlocchi, Mauro Cattaneo
  • Patent number: 6992367
    Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: January 31, 2006
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Pietro Erratico, Enrico Sacchi, Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20060017131
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Application
    Filed: December 20, 2002
    Publication date: January 26, 2006
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona