Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: A computer implemented method of managing processor requests to load data items provides for the classification of the requests based on the type of data being loaded. In one approach, a pointer cache is used, where the pointer cache is dedicated to data items that contain pointers. In other approaches, the cache system replacement scheme is modified to age pointer data items more slowly than non-pointer data items. By classifying load requests, cache misses on pointer loads can be overlapped regardless of whether the pointer loads are part of a linked list of data structures.

Abstract: Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.

Abstract: The present invention is directed to a system and method for implementing a pre-steered instruction cache. The hardware logic that normally steers instructions to specific execution units just prior to execution is moved before the pre-steered instruction cache, so that instructions are pre-steered into that cache. In other words, the instructions can be moved into the instruction cache in such a manner that they are organized in the cache depending on the execution unit(s) to which they will be transmitted. This is done so that an instruction can leave the pre-steered instruction cache and enter the execution unit that can execute it with either minimum or no steering logic involvement. The cache lines of the pre-steered instruction cache are organized into bins such that each bin corresponds to either a single execution unit or a cluster of execution units.

Abstract: How a first result of a first operation compares to a second result of a second operation is identified. The identification may be performed without producing the first result or the second result. The first result or the second result may be selected in response to the identification, and the first operation or the second operation may be performed in response to the selection to produce the selected result. Alternatively, the first operation may be performed to produce the first result and the second operation may be performed to produce the second result. The produced first result or the produced second result may be selected in response to the identification.

Abstract: Methods and apparatus control the loading of a memory buffer. The memory buffer may have a watermark with a first watermark value and can receive an advance indication of a memory service interruption. Based at least in part on the received advance indication of the memory service interruption, the watermark can be modified to have a second watermark value different from the first watermark value.

Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: Methods and apparatus for gathering and scattering data associated with a single-instruction-multiple-data operation are provided. Data is gathered from a main memory, prior to a single-instruction-multiple-data (SIMD) operation on the data, by reading the data into a memory array as columns of data and reading the data out of the memory array as rows of data (or vice-versa). Similarly, after the SIMD operation, resulting data is scattered back to main memory by reading the SIMD results into the memory array as columns of data and reading the data out of the memory array as rows of data (or vice-versa). In this manner, a fast transposition of the SIMD data may occur before and/or after the SIMD operation.

Abstract: Method and apparatus for reducing or eliminating retirement logic in an out-of-order processor are disclosed. Instructions are processed using a processing unit capable of out-of-order processing and having architectural registers having an architectural state. Groups of instructions are prepared for processing by processing unit, wherein within each group to be processed the instructions producing the final state of an architectural register are changed so that they write to an output copy of the architectural state, the instructions reading architectural registers are changed to read from an input copy of the architectural state, and the instructions within each group producing results to architectural registers that would be overwritten by another instruction in the group are changed to write their results to temporary registers.

Abstract: A method and apparatus for eliminating register reads and writes in a scheduled instruction cache. More particularly, the present invention pertains to a method of increasing overall processor performance by implementing a novel pre-cache scheduling operation to eliminate superfluous register reads and writes via a bypass network.

Abstract: A computer implemented method of managing processor requests to load data items provides for the classification of the requests based on the type of data being loaded. In one approach, a pointer cache is used, where the pointer cache is dedicated to data items that contain pointers. In other approaches, the cache system replacement scheme is modified to age pointer data items more slowly than non-pointer data items. By classifying load requests, cache misses on pointer loads can be overlapped regardless of whether the pointer loads are part of a linked list of data structures.

Abstract: A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instructions. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. The transform is then saved. When the sequence of instructions subsequently passes through the pipeline again, the transform is retrieved and used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

Abstract: A method is disclosed in which a higher level instruction having an immediate is read from memory and translated into two lower level instructions. The first is to move a first portion of the immediate to a register, and the second includes a pointer to the register as well as a second portion of the immediate.

Abstract: A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instruction. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. When the sequence of instructions subsequently passes through the pipeline again, the transform is used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

Abstract: Multiplication of complex numbers is performed utilizing a single adder. A “mult_i” instruction includes a first subinstruction to perform a multiplication by +i to perform a first portion of a complex multiplication. Next, a second subinstruction calls a multiplication by −i, and the same adder is used to write results to an output register. The output register contains the results of the complex multiplication.

Abstract: Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.

Abstract: In a method and apparatus for multiplying a complex number in the form of (a+ib), (±1 ±i) the multiplication result is resolved into addition operations providing the real number component of the multiplication result and the coefficient of i in the multiplication result. The addition operations are formed in a plurality of steps, and the terms a and b are combined in each of a pair of arithmetic units in a plurality of steps to provide the real number component and the complex number coefficient. In the preferred form, the multiplication is performed in four pairs of addition, and an operation code determines the signs of each term in each arithmetic unit in each operation.

Abstract: How a first result of a first operation compares to a second result of a second operation is identified. The identification may be performed without producing the first result or the second result. The first result or the second result may be selected in response to the identification, and the first operation or the second operation may be performed in response to the selection to produce the selected result. Alternatively, the first operation may be performed to produce the first result and the second operation may be performed to produce the second result. The produced first result or the produced second result may be selected in response to the identification.

Abstract: Input data is received by an execution unit. One or more current multiply-accumulate operations are performed by the execution unit on the received input data and on input data received by the execution unit for one or more prior multiply-accumulate operations and saved by the execution unit.

Abstract: Method and apparatus for reducing or eliminating retirement logic in an out-of-order processor are disclosed. Instructions are processed using a processing unit capable of out-of-order processing and having architectural registers having an architectural state. Groups of instructions are prepared for processing by processing unit, wherein within each group to be processed the instructions producing the final state of an architectural register are changed so that they write to an output copy of the architectural state, the instructions reading architectural registers are changed to read from an input copy of the architectural state, and the instructions within each group producing results to architectural registers that would be overwritten by another instruction in the group are changed to write their results to temporary registers.