Abstract: A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

Abstract: A memory controller, in one embodiment of the present invention, can control the execution of a memory maintenance operation. A screen blanking event counter can output a first signal. A memory maintenance state circuit can be coupled to the screen blanking event counter to receive the first signal. The memory maintenance state circuit can output a memory maintenance enable signal.

Abstract: Method and apparatus for reducing or eliminating retirement logic in an out-of-order processor are disclosed. Instructions are processed using a processing unit capable of out-of-order processing and having architectural registers having an architectural state. Groups of instructions are prepared for processing by processing unit, wherein within each group to be processed the instructions producing the final state of an architectural register are changed so that they write to an output copy of the architectural state, the instructions reading architectural registers are changed to read from an input copy of the architectural state, and the instructions within each group producing results to architectural registers that would be overwritten by another instruction in the group are changed to write their results to temporary registers.

Abstract: A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.

Abstract: A method of performing a store operation in a computer processor is disclosed. The method issues a store operation that is divided into a pre-fetch micro-operation that loads a needed cache line into a cache memory, and the subsequent store micro-operation stores a data value into the needed cache line that was pre-fetched into the cache memory.

Abstract: Method and apparatus for reducing or eliminating retirement logic in an out-of-order processor are disclosed. Instructions are processed using a processing unit capable of out-of-order processing and having architectural registers having an architectural state. Groups of instructions are prepared for processing by processing unit, wherein within each group to be processed the instructions producing the final state of an architectural register are changed so that they write to an output copy of the architectural state, the instructions reading architectural registers are changed to read from an input copy of the architectural state, and the instructions within each group producing results to architectural registers that would be overwritten by another instruction in the group are changed to write their results to temporary registers.

Abstract: A method of scheduling instructions in a computer processor. The method comprises fetching instructions to create an in-order instruction buffer, and scheduling instruction from the instruction buffer into instruction slots within instruction vectors in an instruction vector table. Instruction vectors are then dispatched from the instruction vector table to a prescheduled instruction cache, and, in parallel, to an instruction issue unit.

Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

Abstract: To increase the efficiency of a pipelined microprocessor, branch prediction is often implemented. Many branch instructions are used to implement program loops with a fixed number of iterations. To accurately predict the branching behavior of branch instructions used to implement program loops a counter based branch prediction system is suggested. The counter based branch prediction system is based on acquiring a final loop count at run time. The final loop count specifies the number of iterations the loop will perform such that the final loop count is used to predict the branching behavior of the branch instruction used to implement the program loops. Three methods for acquiring a final loop count are proposed. Using the suggested counter-based branch prediction method improves the branch prediction rate of the loop related branch instructions and the overall average prediction rate. As a result, this enables the design of higher performing computer pipelines.

Abstract: An advanced register renamer comprises an associative memory having a plurality of entries, each entry storing a representation of a single operation as an expression paired with a corresponding name. The expression and the name are respectively stored in first and second fields of an entry in the memory. Both fields are available for subsequent assembly level operations to use as pattern matches. A means for converting a subsequent operation in the stream to a new operation searches for a match between an expression of the subsequent operation and the first field of a matching entry. Upon finding a match with the expression field in the table, the subsequent operation is renamed to a new operation by replacing the expression with the corresponding name field of the matching entry taken from the associative memory.

Abstract: A computer that performs division in either floating point or integer representation according to a novel algorithm in which a divisor is subtracted from a dividend to generate a first intermediate result. A shifter shifts the intermediate result by N-bits, where N is an integer and 2.sup.N is equal to the radix, to obtain a remainder. A look-up table produces one or more multipliers based upon an upper-bit portion of the remainder and an upper-bit portion of the divisor. The divisor is multiplied by each of the one or more multiples to generate second intermediate results. Each of the secondary intermediate results is then subtracted from the remainder to generate one or more corresponding third intermediate results. A current quotient digit is selected as the largest multiplier which corresponds to the third intermediate result having the smallest possible value (as among all of the third intermediate results).

Abstract: A method and apparatus for executing instructions in a pipelined microprocessor. The method includes re-ordering the set of instructions prior to loading the instructions into an instruction cache. In one embodiment, a re-ordering unit receives the set of instructions as a trace segment made of a set of basic blocks of instructions in a logical order of execution. After being re-ordered, the instructions are presented to the reordered instruction cache in bundles. When an instruction is unavailable, possibly due to an unresolved data dependency, no operation codes (nops) are inserted into the bundle in place of an in place of an instruction, creating fixed length bundles. In a second embodiment, nops are not used. Variable length bundles are produced by using an additional bit(s) per instruction to mark the end of the bundles.

Abstract: A computer-implemented algorithm for dividing numbers involves subtracting the divisor from the divided to generate a first intermediate result, which is then shifted by N-bits to obtain a remainder value. A portion of the remainder and a portion of the divisor are utilized to generate one or more multiples from a look-up table, each of which is multiplied by the divisor to generate corresponding second intermediate results. The second intermediate results are subtracted from the remainder to generate corresponding third intermediate results. The largest multiple which corresponds to a third intermediate result having a smallest positive value is the quotient digit. The third intermediate result that corresponds to the largest multiple is the remainder for the next iteration.

Abstract: A method and apparatus for identifying a sequence of instructions that generate data used by an instruction in a programmed flow of instructions includes a bit array of i lines, where i is an integer, each line representing an instruction in an ordered sequence of instructions. A line in the bit array is made up of a string of bits in which a bit position is set corresponding to a preceding instruction that the instruction is dependent upon. Logic coupled to the bit array generates the string of bits for the next instruction by setting bit positions which correspond to directly dependent instructions and additional bit positions corresponding to the predecessor instructions.