Abstract: Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a network traffic generation system. The system can include a Markov modified Poisson process (MMPP) model, a packet scheduler coupled to the MMP model, a data store of transition windows defined for different defined scales, traffic generation parameter computing logic comprising program code enabled to compute traffic generation parameters for different scales according to respective states identified within different transition windows in the data store for the different scales, and a packet transmitter coupled to the packet scheduler.

Abstract: Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are vertically distributed across multiple banks. To conserve power, the computing devices generally turn off groups of banks, in a sequential manner according to different power states, based on the access latencies of the banks. The computing devices may first turn off groups having the greatest access latencies. The computing devices may conserve additional power by turning of more groups of banks according to different power states, continuing to turn off groups with larger access latencies before turning off groups with the smaller access latencies.

Abstract: Operating a composite array of data storage devices, such as hard disk drives, to conserve power includes storing data in block-level stripes with parity on a composite array including a controller and at least three data storage devices. The composite array includes a hot spare distributed across the data storage devices. The method further comprises placing one of the data storage devices in a standby state, operating the rest of the data storage devices in an active state, and controlling logical operations of the controller and the read and write operations of the active data storage devices to substitute for read and write operations on the standby device. For example, the controller can read redundant data on the active drives and compute data identical to the data on the standby drive to substitute for reading the standby drive. Furthermore, the controller can write a modified version of data on the standby drive to a spare block to substitute for writing to the standby drive.

Abstract: Methods and products are disclosed for analyzing network traffic using an improved Markov Modulated Poisson Process Model with one bursty state and a plurality of idle states that include: establishing a time scale of operation for each state in the improved MMPP model; establishing a transition value for each state in dependence upon the time scale of operation for the state; measuring inter-arrival times between individual packets received in one or more network adapters; and determining a current state for the network traffic independence upon the measured inter-arrival time of a most recently received packet and the transition values.

Abstract: Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions.

Abstract: Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multiple cores, which has cache memory elements coupled with the multiple processors or cores. The cache memory device may track usage of cache lines by using a number of bits. For example, a controller of the cache memory may manipulate bits as part of a pseudo least recently used (LRU) system. Some of the bits may be in a centralized area of the cache. Other bits of the pseudo LRU system may be distributed across the cache. Distributing the bits across the cache may enable the system to conserve additional power by turning off the distributed bits.

Abstract: Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are vertically distributed across multiple banks. To conserve power, the computing devices generally turn off groups of banks, in a sequential manner according to different power states, based on the access latencies of the banks. The computing devices may first turn off groups having the greatest access latencies. The computing devices may conserve additional power by turning of more groups of banks according to different power states, continuing to turn off groups with larger access latencies before turning off groups with the smaller access latencies.

Abstract: Aspects of the invention provide an improved solution for processing packets in a packetized communications network. For example, a next packet in a set of incoming packets placed in a plurality of queues is selected by obtaining a random/pseudo-random search key and identifying one of the plurality of queues based on the search key and a Patricia tree that includes at least one child node for each of the plurality of queues. A greedy algorithm can be used to select an alternative queue should the first selected queue be empty.

Abstract: A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations.

Abstract: A process control method and system including partitioning transmit decisions and certain measurements into one logical entity (Data Plane) and partitioning algorithm computation to update transmit probabilities into a second logical entity (Control Plane), the two entities periodically communicating fresh measurements from Data Plane to Control Plane and adjusted transmit probabilities from Control Plane to Data Plane. The transmit probability may be used in transmit/discard decisions of packets or instructions exercised at every arrival of a packet or instruction. In an alternative embodiment, the transmit probability may be used in transmit/delay decisions of awaiting instructions or packets exercised at every service event.

Abstract: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate.

Abstract: Methods, apparatus, and products are disclosed for analyzing network traffic using an improved Markov Modulated Poisson Process Model with two barrier states that include: retrieving a previous state for the network traffic; measuring inter-arrival times between individual packets received in one or more network adapters; establishing a transition window in dependence upon the measured inter-arrival times, the transition window having a transition value ?Bmax that represents an upper boundary for the inter-arrival times in a bursty state and having a transition value ?Imin that represents a lower boundary for the inter-arrival times in an idle state; retrieving a previous fence value that prevents premature transitions into the idle state or the bursty state; and determining a current state for the network traffic in dependence upon the previous state for the network traffic, an inter-arrival time of a most recently received packet, the transition values, and the previous fence value.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

Abstract: Operating a composite array of data storage devices, such as hard disk drives, to conserve power includes storing data in block-level stripes with parity on a composite array including a controller and at least three data storage devices. The composite array includes a hot spare distributed across the data storage devices. The method further comprises placing one of the data storage devices in a standby state, operating the rest of the data storage devices in an active state, and controlling logical operations of the controller and the read and write operations of the active data storage devices to substitute for read and write operations on the standby device. For example, the controller can read redundant data on the active drives and compute data identical to the data on the standby drive to substitute for reading the standby drive. Furthermore, the controller can write a modified version of data on the standby drive to a spare block to substitute for writing to the standby drive.

Abstract: Power conservation in a redundant array of inexpensive drives (‘RAID array’) that preserve RAID functionality, the RAID array including RAID subarrays of a same RAID specification, including powering off a drive in at least one of the RAID subarrays; responsive to a write request directed to a particular subarray containing a powered off drive, writing data redundantly to a RAID cache that is independent from the subarray having a powered off drive; powering on the powered-off drive; and flushing the written data from the cache to the particular subarray to which it was originally directed.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for dynamic optimization of DRAM controller page policy is provided. The design structure can include a memory module, which can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to memory management and provide a method, system and computer program product for dynamic optimization of DRAM controller page policy. In one embodiment of the invention, a memory module can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank.