Patents by Inventor Ganesh Balakrishnan

Ganesh Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080267065
    Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a network traffic generation system. The system can include a Markov modified Poisson process (MMPP) model, a packet scheduler coupled to the MMP model, a data store of transition windows defined for different defined scales, traffic generation parameter computing logic comprising program code enabled to compute traffic generation parameters for different scales according to respective states identified within different transition windows in the data store for the different scales, and a packet transmitter coupled to the packet scheduler.
    Type: Application
    Filed: June 2, 2008
    Publication date: October 30, 2008
    Inventors: GANESH BALAKRISHNAN, Jorge R. Rodriguez
  • Patent number: 7432175
    Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: October 7, 2008
    Inventors: Diana L. Huffaker, Larry R. Dawson, Ganesh Balakrishnan
  • Publication number: 20080206966
    Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.
    Type: Application
    Filed: January 6, 2006
    Publication date: August 28, 2008
    Inventors: Diana L. Huffaker, Larry R. Dawson, Ganesh Balakrishnan
  • Publication number: 20080130668
    Abstract: Aspects of the invention provide an improved solution for processing packets in a packetized communications network. For example, a next packet in a set of incoming packets placed in a plurality of queues is selected by obtaining a random/pseudo-random search key and identifying one of the plurality of queues based on the search key and a Patricia tree that includes at least one child node for each of the plurality of queues. A greedy algorithm can be used to select an alternative queue should the first selected queue be empty.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Inventors: Ganesh Balakrishnan, Jorge R. Rodriguez
  • Publication number: 20080133864
    Abstract: An apparatus, system, and method are disclosed for caching fully buffered memory (FBM) data. A circuit card is connected to an FBM socket that is configured to receive a FBM. An interface module communicates with a memory controller and at least one FBM via the FBM socket through a plurality of electrical interfaces. A cache controller apportions memory space in the cache memory between each FBM of the at least one FBM according to an apportionment policy. A cache memory transparently stores data from the at least one FBM and the memory controller and transparently provides the data to the memory controller. The cache controller manages coherency between the at least one FBM and the cache memory.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Inventors: Jonathan Randall Hinkle, Aaron Mitchell Richardson, Ganesh Balakrishnan
  • Publication number: 20080123549
    Abstract: Methods, apparatus, and products are disclosed for analyzing network traffic using an improved Markov Modulated Poisson Process Model with two barrier states that include: retrieving a previous state for the network traffic; measuring inter-arrival times between individual packets received in one or more network adapters; establishing a transition window in dependence upon the measured inter-arrival times, the transition window having a transition value ?Bmax that represents an upper boundary for the inter-arrival times in a bursty state and having a transition value ?Imin that represents a lower boundary for the inter-arrival times in an idle state; retrieving a previous fence value that prevents premature transitions into the idle state or the bursty state; and determining a current state for the network traffic in dependence upon the previous state for the network traffic, an inter-arrival time of a most recently received packet, the transition values, and the previous fence value.
    Type: Application
    Filed: September 1, 2006
    Publication date: May 29, 2008
    Inventors: Ganesh Balakrishnan, Jorge R. Rodriguez
  • Publication number: 20080120426
    Abstract: Embodiments of the present invention address deficiencies of the art in respect to TCP processing and provide a novel and non-obvious method, system and computer program product for selectively accelerating TCP connections. In one embodiment of the invention, a method of selectively accelerating TCP connections in TCP/IP based inter-process communications can be provided. The method can include establishing a TCP connection for TCP/IP inter-process communications, observing a block size for the TCP connection, and switching between TCP/IP processing in a host processor and TCP/IP processing in a TOE in a network adapter coupled to the host processor based upon the observed block size exceeding a threshold value.
    Type: Application
    Filed: November 17, 2006
    Publication date: May 22, 2008
    Applicant: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Jorge R. Rodriguez
  • Publication number: 20080056131
    Abstract: Methods and products are disclosed for analyzing network traffic using an improved Markov Modulated Poisson Process Model with one bursty state and a plurality of idle states that include: establishing a time scale of operation for each state in the improved MMPP model; establishing a transition value for each state in dependence upon the time scale of operation for the state; measuring inter-arrival times between individual packets received in one or more network adapters; and determining a current state for the network traffic independence upon the measured inter-arrival time of a most recently received packet and the transition values.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Inventors: Ganesh Balakrishnan, Jorge R. Rodriguez
  • Publication number: 20080043748
    Abstract: Embodiments of the present invention provide a method, system and computer program product for multi-scale network traffic generation. In one embodiment of the invention, a network traffic generation method can be provided. The method can include defining multiple, different scales in an n-state MMPP model to accommodate a full characteristic response of a modeled traffic scenario. The method further can include establishing a transition window for each of the scales and determining a state through the transition window for selected ones of the scales. Finally, the method can include computing an inter-packet time according to the determined state for each of the selected ones of the scales and generating and transmitting packets for the selected ones of the scales utilizing a correspondingly computed inter-packet time.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Applicant: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Jorge R. Rodriguez
  • Publication number: 20070275492
    Abstract: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate.
    Type: Application
    Filed: January 11, 2007
    Publication date: November 29, 2007
    Inventors: Diana Huffaker, Larry Dawson, Ganesh Balakrishnan
  • Patent number: 7274666
    Abstract: A flow control method and system including an algorithm for deciding to transmit an arriving packet into a processing queue or to discard it, or, in the case of instructions or packets that must not be discarded, a similar method and system for deciding at a service event to transmit an instruction or packet into a processing queue or to skip the service event. The transmit probability is increased or decreased in consideration of minimum and maximum limits for each flow, aggregate limits for sets of flows, relative priority among flows, queue occupancy, and rate of change of queue occupancy. The effects include protection of flows below their minimum rates, correction of flows above their maximum rates, and, for flows between minimum and maximum rates, reduction of constituent flows of an aggregate that is above its aggregate maximum. Practice of the invention results in low queue occupancy during steady congestion.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, John P. Chalmers, Clark D. Jeffries, Jitesh R. Nair, Larry W. Nicholson, Ravinder K. Sabhikhi, Raj K. Singh
  • Publication number: 20070162631
    Abstract: Embodiments of the present invention address the deficiencies of the art in respect to application performance and provide a novel and non-obvious data processing method, system and computer program product for selecting between separate hardware implemented and software implemented iSCSI paths to process an input/output request in a data communication environment. In one embodiment, a method for selecting between separate hardware implemented and software implemented iSCSI paths to process an input/output request can include transmitting a stream of requests to access at least one logical block address in at least one storage device in an IP storage system is provided. The utilization of a first processor in a host configured to transmit the stream of requests, where the host provides a first iSCSI implementation can be monitored along with the utilization of a second processor in an adapter coupled to the storage device, where the adapter provides a second iSCSI implementation.
    Type: Application
    Filed: December 28, 2005
    Publication date: July 12, 2007
    Applicant: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Jorge Rodriguez
  • Publication number: 20070160100
    Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, a vertical cavity device can include two types of arrays of misfit dislocations to form high-quality semiconductor layers of the vertical cavity device. The vertical cavity device can be operated at a wavelength of about 1.6-5.0 ?m.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 12, 2007
    Inventors: Diana Huffaker, Larry Dawson, Ganesh Balakrishnan
  • Publication number: 20040246976
    Abstract: A process control method and system including partitioning transmit decisions and certain measurements into one logical entity (Data Plane) and partitioning algorithm computation to update transmit probabilities into a second logical entity (Control Plane), the two entities periodically communicating fresh measurements from Data Plane to Control Plane and adjusted transmit probabilities from Control Plane to Data Plane. The transmit probability may be used in transmit/discard decisions of packets or instructions exercised at every arrival of a packet or instruction. In an alternative embodiment, the transmit probability may be used in transmit/delay decisions of awaiting instructions or packets exercised at every service event.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Applicant: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Everett A. Corl, Clark D. Jeffries, Ravinder K. Sabhikhi, Michael S. Siegel, Raj K. Singh, Rama M. Yedavalli
  • Publication number: 20040196790
    Abstract: A flow control method and system including an algorithm for deciding to transmit an arriving packet into a processing queue or to discard it, or, in the case of instructions or packets that must not be discarded, a similar method and system for deciding at a service event to transmit an instruction or packet into a processing queue or to skip the service event. The transmit probability is increased or decreased in consideration of minimum and maximum limits for each flow, aggregate limits for sets of flows, relative priority among flows, queue occupancy, and rate of change of queue occupancy. The effects include protection of flows below their minimum rates, correction of flows above their maximum rates, and, for flows between minimum and maximum rates, reduction of constituent flows of an aggregate that is above its aggregate maximum. Practice of the invention results in low queue occupancy during steady congestion.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Applicant: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, John P. Chalmers, Clark D. Jeffries, Jitesh R. Nair, Larry W. Nicholson, Ravinder K. Sabhikhi, Raj K. Singh