Patents by Inventor Gang Chen

Gang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11476290
    Abstract: An image sensor includes photodiodes disposed in a pixel region and proximate to a front side of a semiconductor layer. A backside metal grating is formed in a backside oxide layer disposed proximate to a backside of the semiconductor layer. A deep trench isolation (DTI) structure with a plurality of pixel region portions and an edge region portion is formed in the semiconductor layer. The pixel region portions are disposed in the pixel region of the semiconductor layer such that incident light is directed through the backside metal grating, through the backside of the semiconductor layer, and between the pixel region portions of the DTI structure to the photodiodes. The edge region portion of the DTI structure is disposed in an edge region outside of the pixel region. The edge region portion of the DTI structure is biased with a DTI bias voltage.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 18, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen, Kenny Geng
  • Publication number: 20220328545
    Abstract: A pixel circuit includes a photodiode and a floating diffusion disposed in a semiconductor substrate. A transfer gate is disposed between the photodiode and the floating diffusion to transfer photogenerated image charge from the photodiode to the floating diffusion. A dual floating diffusion (DFD) transistor is coupled between the floating diffusion and a DFD capacitor. The DFD transistor includes a DFD gate that includes a planar gate portion disposed over a surface of the semiconductor substrate and a vertical gate portion that extends vertically from the planar gate portion into the semiconductor substrate. The vertical gate portion of the DFD gate is configured to increase a gate to substrate coupling capacitance of the DFD transistor. The gate to substrate coupling capacitance and the DFD capacitor are coupled to increase an effective capacitance associated with the floating diffusion in response to the DFD transistor being turned on.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 13, 2022
    Inventors: Hui Zang, Gang Chen
  • Publication number: 20220320162
    Abstract: A pixel-array substrate includes (i) a semiconductor substrate including a photodiode region and a floating diffusion region, and (ii) a vertical-transfer-gate structure that includes a trench and a gate electrode. The trench is defined by a bottom surface and a sidewall surface of the substrate each located between a front substrate-surface and a back substrate-surface thereof. The trench extends into the substrate. In a cross-sectional plane perpendicular to the front substrate-surface and intersecting the floating diffusion region, the photodiode region, and the sidewall surface, (a) the trench is located between the floating diffusion region and the photodiode region, and (b) a top section of the sidewall surface is adjacent to the floating diffusion region. A gate electrode partially fills the trench such that the top section and a conductive-surface of the gate electrode in-part define a recess located between the floating diffusion region and the gate electrode.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 6, 2022
    Inventors: Hui ZANG, Gang CHEN
  • Publication number: 20220315583
    Abstract: Bridged compounds of Formula (I) and Formula (II), pharmaceutical compositions containing them, methods of making them, and methods of using them including methods for treating disease states, disorders, and conditions associated with MGL modulation, such as those associated with pain, psychiatric disorders, neurological disorders (including, but not limited to major depressive disorder, treatment resistant depression, anxious depression, bipolar disorder), cancers and eye conditions. wherein R2, R3 R4, R5 and R6 are defined herein.
    Type: Application
    Filed: December 23, 2020
    Publication date: October 6, 2022
    Inventors: Michael K. Ameriks, Gang Chen, Chaofeng Huang, Brian Ngo Laforteza, Suchitra Ravula, Wei Zhang
  • Publication number: 20220320175
    Abstract: An uneven-trench pixel cell includes a semiconductor substrate that includes a floating diffusion region, a photodiode region, and, between a front surface and a back surface: a first sidewall surface, a shallow bottom surface, a second sidewall surface, and a deep bottom surface. The first sidewall surface and a shallow bottom surface define a shallow trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A shallow depth of the shallow trench exceeds a junction depth of the floating diffusion region. The second sidewall surface and a deep bottom surface define a deep trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A distance between the deep bottom surface and the front surface defines a deep depth, of the deep trench, that exceeds the shallow depth.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 6, 2022
    Inventors: Hui ZANG, Gang CHEN
  • Patent number: 11462579
    Abstract: A method for forming a transfer gate includes (i) forming a dielectric pillar on a surface of a semiconductor substrate and (ii) growing an epitaxial layer on the semiconductor substrate and surrounding the dielectric pillar. The dielectric pillar has a pillar height that exceeds an epitaxial-layer height of the epitaxial layer relative to the surface. The method also includes removing the dielectric pillar to yield a trench in the epitaxial layer. A pixel includes a doped semiconductor substrate having a front surface opposite a back surface. The front surface forms a trench extending a depth zT with respect to the front surface within the doped semiconductor substrate along a direction z perpendicular to the front surface and the back surface. The pixel has a dopant concentration profile, a derivative thereof with respect to direction z being discontinuous at depth zT.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 4, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11451509
    Abstract: A data transmission method includes determining that a first network address segment overlaps with a second network address segment, and creating at least two subnets on a virtual private cloud (VPC). The first network address segment is a network address segment of a subnet in which a target server is located, and configured to run on the VPC. The first network address segment belongs to a network address segment of the VPC. The second network address segment is a network address segment of a subnet in which a first electronic device is located. A network address segment of one of the at least two subnets on the VPC does not overlap with the first or second network address segment. Network interfaces in the at least two subnets are configured to sequentially forward a data packet being transmitted between the target server and the first electronic device at least two times.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: September 20, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Gang Chen
  • Patent number: 11450777
    Abstract: A back contact structure includes: a silicon substrate including a back including a plurality of recesses disposed at intervals; a first dielectric layer disposed on the back surface of the silicon substrate, the first dielectric layer at least covering the plurality of recesses; a plurality of P-type doped regions and N-type doped regions disposed on the first dielectric layer and disposed alternately in the plurality of recesses; a second dielectric layer disposed between the plurality of P-type doped regions and the plurality of N-type doped regions; and a conductive layer disposed on the plurality of P-type doped regions and the plurality of N-type doped regions
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: September 20, 2022
    Assignee: SOLARLAB AIKO EUROPE GMBH
    Inventors: Kaifu Qiu, Yongqian Wang, Xinqiang Yang, Gang Chen
  • Patent number: 11450696
    Abstract: A pixel circuit includes a photodiode and a floating diffusion disposed in a semiconductor substrate. A transfer gate is disposed between the photodiode and the floating diffusion to transfer photogenerated image charge from the photodiode to the floating diffusion. A dual floating diffusion (DFD) transistor is coupled between the floating diffusion and a DFD capacitor. The DFD transistor includes a DFD gate that includes a planar gate portion disposed over a surface of the semiconductor substrate and a vertical gate portion that extends vertically from the planar gate portion into the semiconductor substrate. The vertical gate portion of the DFD gate is configured to increase a gate to substrate coupling capacitance of the DFD transistor. The gate to substrate coupling capacitance and the DFD capacitor are coupled to increase an effective capacitance associated with the floating diffusion in response to the DFD transistor being turned on.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: September 20, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11448765
    Abstract: An adaptive filtering method of photon counting Lidar for bathymetry is provided in this invention, which includes steps: step S1: adaptively acquiring parameters of elliptic filtering for water surface photon signals; step S2: determining a relationship between filter parameters and elevation of underwater photon signals, and obtaining parameters of the elliptic filtering for photon signal in water column; and step S3: filtering and fitting the water surface photon signals and the underwater photon signals to acquire continuous bathymetry results.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 20, 2022
    Assignee: China University of Geosciences
    Inventors: Lizhe Wang, Yifu Chen, Yuan Le, Gang Chen, Weitao Chen
  • Publication number: 20220293596
    Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chieh-Ping WANG, Tai-Chun Huang, Yung-Cheng Lu, Ting-Gang Chen, Chi On Chui
  • Publication number: 20220285529
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
  • Publication number: 20220282356
    Abstract: The present invention relates to an aluminum matrix composite (AMC), and particularly to a method and apparatus for preparing an AMC with a high strength, a high toughness, and a high neutron absorption. The present invention combines a high-neutron-absorption and highly stable micro-B4C extrinsic reinforcement with an in-situ nano-reinforcement containing elements B, Cd, and Hf and having high neutron capture ability, achieves efficient absorption of neutrons by using the large cross-sectional area of the micro-reinforcement, achieves effective capture of rays penetrating gaps of the micro-reinforcement by means of the highly dispersed in-situ nano-reinforcement, and significantly improves the toughness of the composite material by means of the high-dispersion toughening effect of the nano-reinforcement, obtaining a particle-reinforced aluminum matrix composite (PAMC) having high toughness and high neutron absorption.
    Type: Application
    Filed: October 22, 2020
    Publication date: September 8, 2022
    Applicant: Jiangsu University
    Inventors: Xizhou KAI, Yutao ZHAO, Yanjie PENG, Gang CHEN, Xiaojing XU, Lin WU, Shuoming HUANG, Ruikun CHEN
  • Publication number: 20220276538
    Abstract: An array substrate and a liquid crystal display panel thereof. The array substrate includes a substrate having a plurality of pixel regions arranged in an array. Each of the pixel regions (120a) includes: a first electrode, a second electrode, an insulation protrusion, and a reflection electrode. An electric field is fit to form between the second electrode and the first electrode, and an electric field is also fit to form between the reflection electrode and the second electrode. The second electrode includes a slit electrode, which includes a plurality of slit portions and a plurality of electrode portions each arranged between adjacent slit portions. The electrode portion at least includes a first strip-shaped portion and a second strip-shaped portion. An extension direction of the first strip-shaped portion intersects with that of the second strip-shaped portion, and the first strip and second strip-shaped portions of each electrode portion are connected at a corresponding bending portion.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 1, 2022
    Inventors: Yanli ZHAO, Xiaoji LI, Hailong WU, Gang CHEN, He SUN, Di WANG, Yu WANG
  • Publication number: 20220278000
    Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: May 13, 2022
    Publication date: September 1, 2022
    Inventors: Chieh-Ping Wang, Ting-Gang Chen, Bo-Cyuan Lu, Tai-Chun Huang, Chi On Chui
  • Patent number: 11430908
    Abstract: A method for removing an undesired coating from a front face of a crystalline silicon solar cell includes: S1: depositing an Al2O3 film, an SiO2 film, and an SiNx film on a back face of a silicon wafer to form a backside passivation film, and forming an undesired coating on an edge of the front face of the silicon wafer; S2: preparing an aqueous film on a surface of the backside passivation film of the product obtained in S1; S3: passing the product obtained in S2 through an acid tank to remove the undesired coating; S4: passing the product obtained in S3 through a water tank to remove a residual treatment solution; and S5: drying the product obtained in S4.
    Type: Grant
    Filed: April 11, 2021
    Date of Patent: August 30, 2022
    Assignee: ZHEJIANG AIKO SOLAR ENERGY TECHNOLOGY CO., LTD.
    Inventors: Huimin Wu, Xiaoming Zhang, Jiebin Fang, Kang-Cheng Lin, Daneng He, Gang Chen
  • Patent number: 11419259
    Abstract: A directional garlic seed throwing mechanism includes a base, a rotating device, a vision sensor, a seed throwing guide plate, a seed guide pipe and a plurality of bulbil adjusting devices. The rotating device includes a rotating motor detachably connected to the base and a turntable connected to an output end of the rotating motor. The seed throwing guide plate is arranged on the turntable to enable garlic seeds of seed containing bowls to fall into the seed guide pipe. The seed guide pipe has an upper port right below the bulbil adjusting devices and arranged on the base. An even number of the bulbil adjusting devices are fixed on the turntable uniformly and symmetrically and include the seed containing bowls and bulbil direction control devices for driving the bowls to rotate 180 degrees.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 23, 2022
    Assignees: SHANDONG ACADEMY AGRICULTURAL MACHINERY SCIENCES, Shandong University
    Inventors: Jingxin Shen, Yitian Sun, Yongjia Sun, Gang Chen, Qing Long Li, Xian Ying Feng, Jun Zhou, Peng Yan
  • Patent number: 11417701
    Abstract: A CMOS image sensor has an array of photodiode cells, the photodiode cells each include four buried photodiodes coupled by vertical transfer gate transistors to a single floating node diffusion. Each cell also has a reset transistor coupled to the floating node diffusion, a source follower transistor having gate coupled to the floating node diffusion, and a read select transistor coupled to the source follower transistor. The reset transistor, source follower transistor, and read select transistor have predominately gate and shape edges oriented at an angle greater than 30-degrees and less than 60-degrees from a line extending along an entire horizontal row of photodiodes of a photodiode array of the image sensor and are formed vertically above, and in the same integrated circuit as, the photodiodes of the photodiode array.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 16, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11412977
    Abstract: Systems and methods are described for computing a quantitative index that characterizes Alzheimer's disease (“AD”) risk events based on a temporally ordered sequence of biomarker events. In general, the systems and methods described here implement a modified event-based probabilistic (“EBP”) model to calculate the risk index from biomarker data.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 16, 2022
    Assignee: The Medical College of Wisconsin, Inc.
    Inventors: Shi-Jiang Li, Guangyu Chen, Gang Chen
  • Patent number: D964426
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: September 20, 2022
    Assignee: Danfoss Power Solutions (Zhejiang) Co. Ltd.
    Inventors: Zhimin Guo, Xiaogang Wang, Gang Chen, Shujun Shen, Hui Jin