Patents by Inventor Gary B. Bronner
Gary B. Bronner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220238159Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.Type: ApplicationFiled: January 3, 2022Publication date: July 28, 2022Inventors: Gary B. Bronner, Brent Steven Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
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Patent number: 11329010Abstract: An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.Type: GrantFiled: April 2, 2020Date of Patent: May 10, 2022Assignee: Cryptography Research, Inc.Inventors: Scott C. Best, Ming Li, Gary B. Bronner, Mark Evan Marson
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Patent number: 11244727Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.Type: GrantFiled: November 12, 2015Date of Patent: February 8, 2022Assignee: Rambus Inc.Inventors: Gary B. Bronner, Brent S. Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
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Publication number: 20200328163Abstract: An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.Type: ApplicationFiled: April 2, 2020Publication date: October 15, 2020Inventors: Scott C. BEST, Ming LI, Gary B. BRONNER, Mark Evan MARSON
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Patent number: 9966142Abstract: A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.Type: GrantFiled: May 6, 2009Date of Patent: May 8, 2018Assignee: Rambus Inc.Inventors: Brent S. Haukness, Ian Shaeffer, Gary B. Bronner
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Patent number: 9564225Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.Type: GrantFiled: October 8, 2015Date of Patent: February 7, 2017Assignee: Rambus Inc.Inventors: Mark D. Kellam, Brent Steven Haukness, Gary B. Bronner, Kevin Donnelly
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Patent number: 9490002Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.Type: GrantFiled: July 16, 2015Date of Patent: November 8, 2016Assignee: Rambus Inc.Inventors: Frederick A. Ware, Brent S. Haukness, Scott C. Best, Gary B. Bronner
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Patent number: 9437280Abstract: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping.Type: GrantFiled: October 3, 2014Date of Patent: September 6, 2016Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Gary B. Bronner
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Publication number: 20160071608Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.Type: ApplicationFiled: November 12, 2015Publication date: March 10, 2016Inventors: Gary B. Bronner, Brent S. Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
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Publication number: 20160027498Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.Type: ApplicationFiled: July 16, 2015Publication date: January 28, 2016Inventors: Frederick A. Ware, Brent S. Haukness, Scott C. Best, Gary B. Bronner
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Publication number: 20160027515Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventors: Mark D. Kellam, Brent Steven Haukness, Gary B. Bronner, Kevin Donnelly
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Patent number: 9202572Abstract: In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range.Type: GrantFiled: December 5, 2013Date of Patent: December 1, 2015Assignee: Rambus Inc.Inventors: Gary B. Bronner, Brent S. Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
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Patent number: 9177655Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.Type: GrantFiled: January 1, 2014Date of Patent: November 3, 2015Assignee: Rambus Inc.Inventors: Mark D. Kellam, Brent Steven Haukness, Gary B. Bronner, Kevin Donnelly
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Publication number: 20150103605Abstract: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping.Type: ApplicationFiled: October 3, 2014Publication date: April 16, 2015Applicant: RAMBUS INC.Inventors: Thomas Vogelsang, Gary B. Bronner
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Patent number: 8885423Abstract: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping.Type: GrantFiled: November 19, 2010Date of Patent: November 11, 2014Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Gary B. Bronner
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Publication number: 20140254286Abstract: In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range.Type: ApplicationFiled: December 5, 2013Publication date: September 11, 2014Applicant: Rambus Inc.Inventors: Gary B. Bronner, Brent S. Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
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Publication number: 20140247656Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.Type: ApplicationFiled: January 1, 2014Publication date: September 4, 2014Applicant: Rambus Inc.Inventors: Mark D. Kellam, Brent Steven Haukness, Gary B. Bronner, Kevin Donnelly
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Patent number: 8716780Abstract: A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.Type: GrantFiled: August 26, 2010Date of Patent: May 6, 2014Assignee: Rambus Inc.Inventors: Mark D. Kellam, Gary B. Bronner
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Patent number: 8644078Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.Type: GrantFiled: January 29, 2010Date of Patent: February 4, 2014Assignee: Rambus Inc.Inventors: Mark D. Kellam, Brent Steven Haukness, Gary B. Bronner, Kevin Donnelly
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Patent number: 8614485Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.Type: GrantFiled: December 23, 2008Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li