Abstract: An improved SRAM resistor structure having implanted therein ions of an material in the surface layer of a drain junction region juxtaposed to an overlying metal contact layer providing the benefits of high resistance, low energy consumption, a single ion implantation step in an easily controlled process while producing a precise resistance desired and a method of making the SRAM resistor structure.

Abstract: An EPROM memory cell and its fabrication are described. The semiconductor substrate is a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate includes a first conductive material, a second layer of dielectric material, and a second conductive layer. A sidewall dielectric spacer is formed adjacent to an edge of the gate. Ions are implanted into the substrate of a species of an opposite conductivity type, at a substantial acute angle relative to a vertical angle with respect to the substrate, with the spacer protecting the substrate from ion implantation adjacent to the gate. Alternatively, the sidewall can be formed subsequent to the second deposition of doping ions at an acute angle.

Abstract: A method for fabricating semiconductor devices with localized pocket implantation wherein narrow gaps between a masking layer and a gate electrode are formed prior to pocket implantation. The narrow gaps are formed by removing an isolation layer between the masking layer and the gate electrode. The localized pocket implantation forms small localized pocket regions in a substrate to minimize the areas of source-substrate and drain-substrate junctions, thus reducing the junction capacitance.

Abstract: A method of fabricating a super thin O/N/O stacked dielectric by oxidizing a thin nitride layer in low pressure oxygen for high-density DRAMs is disclosed. A thin nitride layer with a thickness of approximately 20 .ANG. to 60 .ANG. is formed over the surface of a silicon substrate. The nitride layer is oxidized in pure oxygen ambient of 0.01 Torr to 76 Torr at a temperature from 750.degree. C. to 950.degree. C. for approximately 10 to 60 minutes. A super thin oxide/nitride/oxide (O/N/O) stacked dielectric exhibiting a low leakage current and high reliability for use in high-density DRAMs is formed by the aforementioned low-pressure dry-oxidation procedure.

Abstract: The structural configuration of an improved submicron metal-oxide semiconductor field-effect transistor and the method of its fabrication are disclosed. A field oxidation procedure is employed to increase the thickness of the gate oxide layer at both of its ends. The result is decreased gate and drain overlapping region parasitic capacitance, as well as decreased gate-induced drain-leakage current, due to the reduction of the electric field intensity in the overlapping region at which the thickness is increased. The resulting metal-oxide semiconductor field-effect transistor, therefore, is provided with improved operating characteristics for use at high frequencies.

Abstract: A split-gate memory cell and its fabrication are described. The semiconductor substrate is of a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate comprises a first layer of conductive material, a second layer of dielectric material, and a third layer also composed of a second conductive layer. First and second sidewall dielectric spacers are formed adjacent to the first edge and the second opposing edge, respectively of the gate. Ions are implanted into the substrate. Those ions comprise a species of an opposite conductivity type. The ions are implanted at a substantial acute angle relative to a vertical angle with respect to the substrate. A third conductive material is deposited upon the second conductive layer and the first and second sidewall dielectric spacers. The third conductive material is in electrical contact with the second conductive layer.

Abstract: This patent discloses a split-gate flash memory cell having a vertical isolation gate and a process for making it. The inventive cell has better control and a denser memory array than conventional cells. By use of a vertical isolation gate a smaller cell size is obtained. The memory cell has a floating gate transistor formed in a substrate having a channel extending underneath a floating gate, and a vertical isolation transistor formed in the substrate having a channel parallel to a trench holding a portion of a polysilicon control gate and orthogonal to the channel of the floating gate transistor.

Abstract: A dual photo-resist process for fabricating capacitor plates of a DRAM is disclosed including the step of forming a capacitor on a semiconductor IC surface. A first plurality of photo-resist regions which are separated from each other by spaces are then formed on the capacitor plate layer. At least one second photo-resist region is then formed on the capacitor plate layer which partially fills a space between, and is adjacent to one of, two of the first photo-resist regions. The capacitor plate layer is then etched below the spaces between the first and second photo-resist regions to form a plurality of individual capacitor plates including one capacitor plate for each DRAM cell.

Abstract: A method of forming a MOS device having a localized anti-punchthrough region, which is adjacent to but is not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for a subsequent implantation process to form the localized anti-punchthrough region.

Abstract: A floating gate EPROM has surface source and drain regions, with a trench between the source and drain regions containing the floating and control gates. A thin tunneling oxide layer is located at the bottom of the trench and on the sidewalls of the trench adjacent the source and drain regions, with thicker gate oxide elsewhere in the trench.

Abstract: The present invention provides a method of fabricating a DRAM cell capacitor having an improved capacitance by increasing the surface area of the electrode plate. First, a first insulating layer, a second insulating layer, and a barrier layer are formed sequentially on a semiconductor substrate having source/drain regions. Next, a portion of the barrier layer is etched to form a first contact opening over one of the source/drain regions. A first sidewall spacer is formed on the sidewall of the first contact opening of the barrier layer. Similarly, a second contact opening is formed by etching the second insulating layer using the barrier layer and the first sidewall spacer as a mask, and a second sidewall spacer is formed on the sidewall of the second contact opening of the second insulating layer.

Abstract: A process of fabricating a split gate flash memory cell first forms a stacked-gate structure on a face of a substrate. The stacked-gate structure includes a tunnel oxide, a polysilicon floating gate, an inter-poly dielectric and a first polysilicon control gate. A drain region is formed into the substrate at one side of the stacked-gate structure, and is self-aligned with the stacked-gate structure. Thermal oxidation is performed to form sidewall oxides on the sidewalls of the stacked-gate structure, and gate oxide on the substrate. A second polysilicon control gate is deposited over the first polysilicon control gate, sidewall oxides and gate oxide, and is connected with the first polysilicon control gate to form a common control gate. A source region is formed in the substrate at another side of the stacked-gate structure, and is self-aligned with the substantially upright portion of the second polysilicon control gate located at the another side of the stacked-gate structure.

Abstract: A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.

Abstract: A method for fabricating an MOSFET device on a lightly doped semiconductor substrate with a first dielectric layer thereon comprises forming a floating gate layer over the first dielectric layer. The floating gate layer is formed into a floating gate line. A doped source region and a doped drain region in the substrate are formed by ion implantation adjacent to the periphery of the floating gate line. The first dielectric layer is etched, exposing the surface of the substrate and the surface of the source region and the drain region aside from the floating gate line. Textured dielectric spacers are formed about the periphery of the floating gate line. Polycrystalline spacers are formed about the periphery of the polysilicon oxide dielectric spacers in electrical contact with the doped regions.

Abstract: A method is provided for fabricating a MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.

Abstract: A new method of obtaining a consistent controllable tunnel oxide near the source/drain edge of a contactless memory cell is described. A thick gate oxide layer is grown on a semiconductor substrate. A first polysilicon layer is deposited overlying the thick gate oxide layer. A silicon nitride layer followed by a silicon oxide layer are deposited overlying the first polysilicon layer. The silicon oxide, silicon nitride, and first polysilicon layers are patterned and etched. Arsenic ions are implanted through the thick gate oxide layer into the substrate to form buried source and drain bit lines within the substrate. A second layer of silicon nitride is deposited over the patterned layers and anisotropically etched to form sidewall spacers. SATO (self-aligned thick oxide) oxidation is performed over the N+ area. The silicon nitride spacers are etched away whereby a portion of the thick gate oxide underlying the spacers is exposed. The silicon oxide layer is removed along with the exposed thick gate oxide.

Abstract: A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers, improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

Abstract: A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.

Abstract: A self-aligned coding process for mask ROM is disclosed. First, a substrate having a plurality of bit-lines formed therein, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together construct an array of memory cells, is provided. Next, a barrier layer is formed on the word-lines. A silicon dioxide layer is formed on the gate oxide between the word-lines by using liquid phase deposition, wherein the thickness of the silicon dioxide layer is larger than that of the word-lines. Then, the barrier layer is removed. A mask layer is formed on the substrate exposing parts of the memory cells that will be programmed. Finally, impurities are implanted into the substrate not covered by the mask layer and the silicon dioxide layer to make the memory cells that will be programmed operating in a first state, and leave other non-programmed memory cells operating in a second state.

Abstract: A method of fabricating MOS device with anti-punchthrough region is described. The area of anti-punchthrough region is reduced by using the control of double spacers. Moreover, this method utilizes the buried contact structure to connect to the source/drain regions, which not only reduces the contact resistance but also reduces the device size since the metal contact can be provided over the field oxide layer instead of the source/drain regions. Hence, this method is capable of fabricating submicron devices for semiconductor integrated circuit.