Abstract: A new capacitor configuration and its method of manufacture. The capacitor, which may be used with DRAM cells, is made on a substrate having a gate electrode, source/drain areas, and a first insulating layer containing a first contact opening formed therein. A first conducting layer is formed overlying the insulating layer and connected to the source/drain areas through the first contact opening. Next, the steps are performed repeatedly as follows. A first dielectric layer, a second conducting layer, a second dielectric layer, and a third conducting layer are sequentially formed overlying the first conducting layer and the first insulating layer. Portions of the third conducting layer, the second dielectric layer, and the second conducting layer are etched to form a second contact opening. Sidewall spacers are formed on the side walls of the second contact opening.

Abstract: A process for fabricating a flash EEPROM device in a semiconductor substrate. The flash EEPROM device includes a number of memory cells each built around a transistor. A shielding layer is first formed over the surface of the substrate extending in a first direction for defining bit lines for the memory cells of the device. The shielding layer is then utilized as a shielding mask for implementing an oxidation procedure, thereby forming field oxide layers over the surface of the substrate of the first conductivity type, whereby the shielding layer straddles the field oxide layers. Then the field oxide layers are utilized as the shielding mask for implanting impurities into the substrate, thereby forming the bit lines. The shielding layers then are utilized as the shielding mask for removing the field oxide layers while preserving the portions of the field oxide layer underneath the shielding layers, thereby forming trenches revealing the substrate. The shielding layers are then removed.

Abstract: A method of fabricating semiconductor integrated circuit non-volatile memory devices having memory cell isolation between the memory cells without increasing device dimension. Active regions are defined by forming field oxide layers on a on semiconductor substrate of a first type. Lightly-doped regions of the first type are formed underneath field oxide layers. Additional heavily-doped regions of the first type are formed within each of the lightly-doped regions. Active regions on the semiconductor substrate are implanted with impurities of a second type to form drains and sources for the memory cells. Floating gate layers are formed on tunnel oxide layers, the tunnel oxide layers separating the floating gate layers from the active regions. The presence of the lightly-doped region improves the breakdown voltage, while the additional heavily-doped regions within each of the lightly-doped regions increases threshold and punchthrough voltages for the inherent parasitic transistors of the memory device.

Abstract: An EEPROM cell is made by forming a first dielectric layer on a substrate, forming a tunnel mask with an tunnel opening used for etching the dielectric layer to form a tunnel window, doping a region of the substrate through the tunnel window and stripping the tunnel mask. A spacer frame is made about the perithery of the window over the first doped region of the substrate. A second dielectric layer is formed over the first doped region within the spacer frame which is then removed. Tunnel oxide is deposited on the exposed surface of the first doped region, a floating gate layer is deposited, mask and etched. The mask is stripped Ions are implanted into buried N+ source/drain regions through exposed surfaces of the gate oxide near the floating gate. A blanket interconductor layer covers the device. A control gate layer is deposited, mask and etched. The control gate mask is then removed.

Abstract: A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

Abstract: A programmable read-only memory (PROM) and a method of fabrication are described. A plurality of bit-lines of a first conductivity type are formed in a semiconductor substrate and are spaced apart along a first direction. A dielectric layer is disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of vias at predetermined positions above the bit-lines. A plurality of word-lines of a second conductivity type are disposed on the dielectric layer and spaced apart along a second direction substantially orthogonal to the first direction. A control layer is disposed within the vias and sandwiched between the bit-lines and the word-lines, wherein each crossing region of the bit-lines and the word-lines with the control layer disposed there between define a memory cell of the programmable read-only memory.

Abstract: A semiconductor device includes a semiconductor substrate doped with a first conductivity type. The substrate has a surface, with a parallel array of word lines ion implanted as regions in the surface of said substrate. The N+ word lines are of the opposite conductivity type from the P- substrate. A dielectric layer, formed on the substrate above the word lines, is covered with a polysilicon layer doped with a P- conductivity type. A second dielectric layer covers the polysilicon layer. A parallel array of N+ conductivity regions form doped N+ bit lines in the polysilicon layer. Above the N+ bit lines are formed alternating strips of planarized silicon nitride separated by silicon dioxide strips which are covered by a BPSG layer. An etched code pattern is formed extending through the polysilicon layer in a predetermined region providing an encoded RON.

Abstract: A process for fabricating a MOS transistor having a full-overlap lightly-doped drain is disclosed. The MOS transistor is fabricated on a semiconductor silicon substrate that has formed thereon a field oxide layer that defines the active region of the MOS transistor. A field oxide layer is first used as the shielding mask for implanting impurities into the active region thereby forming a lightly-doped region. A shielding layer is then formed with an opening over the surface of the substrate. The opening has two sidewalls that generally define the channel region for the MOS transistor. A gate insulation layer is then formed over the surface of the substrate within the confinement of the opening. Conducting sidewall spacers are then formed over the sidewalls of the opening. The shielding layer and conducting sidewall spacers are then utilized as the shielding mask for implanting impurities into the lightly-doped region, thereby forming the channel region for the MOS transistor.

Abstract: A method is desired for making an array of dynamic random access memory (DRAM) cells having stacked capacitors with increased capacitance. The method involves forming a bottom electrode having a lower and upper fin-shaped portion in which a vertical extension is formed on the lower fin-shape portion at the same time that the upper fin is formed. This increases the capacitance of the stacked capacitor. The bottom electrode is formed by patterning a thick expendable silicon oxide layer and an underlying doped polysilicon layer (lower fin portion). Another polysilicon layer (upper fin portion is conformally coated over the thick insulating layer and patterned with an etch mask, which is smaller than the patterned insulating layer. An anisotropic etch is performed that forms the upper fin portion, the vertical extension on the lower fin portion and electrically isolates the array of electrodes.

Abstract: A process for fabricating MOS transistor devices on a semiconducting substrate first forms a shielding layer, having an opening with sidewalls therein, over the substrate to define a channel region. Then, first sidewall spacers are formed on the sidewalls and a gate insulating layer is formed within the confinement of the first sidewall spacers. Next, a gate electrode is formed over the gate insulating layer, and then the first sidewall spacers are removed, thereby forming trenches between the edges of the gate electrode and the shielding layer. Afterwards, lightly-doped regions of a second conductivity type are formed beneath the trenches and doped regions of the first conductivity type are formed to surround the lightly-doped regions. After removing the shielding layer, second sidewall spacers are formed to overlie the lightly-doped regions.

Abstract: A ROM coding method with a self-aligned implantation. First, a non-coded mask ROM with a semiconductor substrate, a plurality of bit-lines formed on the semiconductor substrate, a gate oxide formed over the semiconductor substrate and the bit-line, and a plurality of word-lines formed above the gate oxide, which together form memory cells, is provided. Before the word-lines are formed, a barrier material is applied over spacing strips between the locations where the word-lines are to be formed. The barrier material serves as a mask through which impurities are implanted into the substrate to selectively program the memory cells to operate in either a first or second conduction state.

Abstract: A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. This reduces bit line sheet resistance and increases the punch-through voltage between adjacent bit lines.

Abstract: A process of fabricating the storage capacitor for a dynamic random access memory cell which includes a transistor with gate electrode and source/drain regions on a surface of a substrate. The process forms a polysilicon layer which is coupled to one of the source/drain regions, over the transistor structure. A mask is formed to cover the planned capacitor area, and then the non-masked portion of the polysilicon layer is removed. Liquid phase deposition oxide is formed on the area not masked by the mask, and then the mask is stripped. A polysilicon sidewall spacer is formed on the sidewalls of the LPD oxide, and connects with the remaining polysilicon layer to jointly form a first capacitor electrode. The LPD oxide is removed, followed by forming a dielectric layer along the surface of the first capacitor electrode. A second capacitor electrode made from polysilicon is formed along the surface of the dielectric layer to complete the storage capacitor structure.

Abstract: A method of forming doped well regions for FETs and doped field regions for channel stops to prevent surface inversion under the field oxide was achieved using a single ion implantation. The method involves forming a patterned silicon oxide layer over the field regions by selective deposition using liquid phase deposition (LPD) and a patterned photoresist mask. An ion implantation through the thick LPD silicon oxide layer over the field regions and through a thinner silicon nitride layer over the well regions resulted in a shallow doped field region and a deep doped well region. After removing the LPD oxide in HF, LOCOS was used to form the field oxide drive-in the dopant and anneal out the implant damage. After removing the silicon nitride layer over the well regions, gate oxides, polysilicon gate electrodes, and source/drains areas are formed to complete the FETs. The LPD process resulted in a doped field region self-aligned to a doped well region that required fewer masking and implant steps.

Abstract: A method of manufacturing mask ROM using LPD to obtain the advantages of self-alignment. The bit line resistance and bit line capacitance are both reduced due to prevention of counterdoping but the device breakdown voltage is maintained. Oxide regions are deposited over the bit lines by LPD to form mesas thereon. When a conductive layer is deposited, recesses in the conductive layer occur in channel regions between neighboring mesas. When programming the device by implanting impurities, they automatically concentrate in the channel regions between the bit lines, in a self-aligned manner, therefore counterdoping of the bit lines is prevented.

Abstract: A random access memory (RAM) cell capacitor and its method of fabrication. A bottom electrode plate of the capacitor is provided with a plurality of islands disposed on the surface thereof so as to attain an increase in the capacitance thereof.

Abstract: A method, and resultant structure, for manufacturing ROM (Read Only Memory) integrated circuits that may be coded, or programmed, after metallization, is described. A plurality of parallel bit lines is formed in a semiconductor substrate. There is a thin insulating layer over the substrate. A plurality of parallel word lines is formed over the thin insulating layer, arranged orthogonally to the bit lines. Gate electrodes of a single conductive material are in coded regions under the word lines, over the thin insulating layer, and between the bit lines, where a ROM code etch has been performed, such that there is a gap between the single conductive material and the word lines. The ROM code etch is performed by an RCA etch of titanium or titanium nitride previously formed between the single conductive material and the word lines. Gate electrodes of two layers of conductive material are in uncoded regions connected to and under the word lines, over the thin insulating layer, and between the bit lines.

Abstract: A manufacturing process for a MOSFET device on a lightly doped semiconductor substrate comprises forming a dielectric layer on the substrate, a floating gate layer over the dielectric layer, a sacrificial layer on the floating gate layer, and a split-gate channel mask patterned with openings over the sacrificial layer. Etch the sacrificial layer to remove material beneath mask openings and etch the floating gate layer to remove material beneath mask openings to form a self-aligned channel mask for ion implanting the source/drain regions of the device. Overetch the floating gate layer to form a floating gate and ion implant doped source/drain regions. Remove the channel mask and the remainder of the sacrificial layer. Form a drain side mask and ion implant a drain side N- region into the substrate. Form a blanket interpolysilicon dielectric layer, a deposit of a control gate layer over the interpolysilicon layer with a control gate mask, and etch the control gate layer through the control gate mask openings.

Abstract: This invention describes a device structure and a method of forming the device structure using a polysilicon spacer formed on the edges of the gate electrode forming a gate structure with a cavity. The channel area is self aligned through this cavity. A fully overlapped Lightly-Doped-Drain structure is used to improve device characteristics for submicron devices. A deep boron implant region, self aligned through the gate structure, is used to improve punch through voltage.

Abstract: A MOSFET device is formed on a lightly doped semiconductor substrate, starting by forming a first dielectric layer on the substrate; forming a mask with an array of openings therein over the dielectric layer, and forming thick silicon dioxide regions through openings in the mask. Dopant is ion implanted into the substrate through the mask between the thick silicon dioxide regions to form an array of buried bitline conductors. Perform an etch back through the mask of the thick silicon dioxide regions removing material to form channel openings in the thick silicon dioxide regions down to the substrate. Then deposit a gate oxide layer over the exposed substrate, forming a conformal array of conductors over the device extending down into the channel openings forming sidewalls therein narrowing the channel openings. Then, form a ROM code mask over the device with a ROM code opening over one of the channel openings; and ion implant dopant into the ROM code opening.