Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the change signal to toggle, and the trace logic notes the state change in the signal. It then exports the internal state presented to it. Once it completes the export, it changes the state of advance and the process begins anew.

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.

Abstract: Control commands are transmitted via an emulation interface holding a test clock signal at a constant value and switching a test mode select signal a number of times corresponding to the control command. A receiving system counts switches of the test mode select signal switches while the test clock is constant and interprets the number of switches as a corresponding control command.

Abstract: A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

Abstract: A method and system of identifying overlays used by a program. The overlays may be executable overlays (e.g., overlay programs and dynamically linked library programs), or the overlays may be data sets. Depending on the number of overlays and/or the type of information used to identify the overlays, an indication of the identity of the overlays may be written to a register (whose contents are inserted into the trace data stream), or the indication may comprise an entry in a log buffer and an index value written to the register (again whose contents are inserted into the trace data stream, and where the index value identifies the entry in the log buffer).

Abstract: Stall monitoring systems and methods are disclosed. Exemplary stall monitoring systems may include a core, a memory coupled to the core, and a stall circuit coupled to the core. The stall circuit is capable of separately representing at least two distinct stall conditions that occur simultaneously and conveying this information to a user for debugging purposes.

Abstract: A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system (the first control segment including control information that selects an active communications protocol from a plurality of communications protocols); sequencing at least part of the first and second systems through a series of states that control the active communications protocol based upon the control information in the first control segment; and exchanging a data segment of the message (after the first control segment) between the first system and the second system The series of states represents inert sequences to the remaining communications protocols of the plurality of communications protocols that were not selected as active.

Abstract: An information carrier medium containing debugging software that, when executed by a processor, causes the processor to generate an event signal and an event code and provide the event signal and the event code to an event detection logic coupled to the processor. The event detection logic is adapted to generate a plurality of events, where a number of events generated corresponds to the event code.

Abstract: While tracing program execution in the device under test, the trace receiver is connected to the device through a dedicated trace port, and through the common memory interface. Trace data is received through the trace port, and is written into memory through the common memory interface. The data may be read real time while being recorded, or after recording has ceased.

Abstract: Last stall information is transmitted if the last stall standing function is enabled, one of the stall elements was active during the last clock cycle, no stall condition exists during the current cycle and the stall threshold has been met. Last stall standing operation provides a label associated with each stall period that exceeds a specified threshold. This provides the means to filter out some stall bursts to reduce trace bandwidth.

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.