Abstract: Multiple debug tools interacting with the same target system must be interconnected to allow communication between the debug tools. This interconnection may be accomplished by connections on the motherboard, interconnecting at the connector level, or direct connections between the applicable debug tools.

Abstract: With multiple trace data sources, each source may be routed to n destinations. The source identifies the destination of its data to trace merge logic along with its source ID and data. Packing logic uses this routing information to pack the data for delivery to the desired destination, merging this data with other data destined for the same destination.

Abstract: The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the change signal to toggle, and the trace logic notes the state change in the signal. It then exports the internal state presented to it. Once it completes the export, it changes the state of advance and the process begins anew.

Abstract: A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups of processor events in order to gain a full understanding of how code is being executed by the processor.

Abstract: The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple data sources, including building one or more single-source data words by iteratively selecting a data source, writing data from the data source to each data section within a single-source data word if enough data is available to fill the single-source data word, copying a data bit of the single-source data word to a data bit within a start word, and clearing the data bit of the single-source data word; and including transmitting the one or more single-source data words after transmitting both a start word and one or more multi-source data words within the same data frame The data written into the one or more single-source data words and the data most recently written into the one or more multi-source data words originate from the same data source.

Abstract: A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive input from a user of the software, the input comprising data and a cache identifier. The processor also transfers the data and cache identifier to a circuit logic that is adapted to write to caches in a cache system coupled to the circuit logic. The processor also causes the circuit logic to write the data to a cache in the cache system that corresponds to the cache identifier.

Abstract: During trace recording, on-chip trace export mechanisms may schedule output from multiple sources out of order of execution. This makes the exact arrival of trace information in the receiver imprecise. Time of the day or time stamp information may be placed in the trace stream itself to assure correct timing, and represented as a control word. This may be done periodically or at the first empty slot after some period has elapsed.

Abstract: Navigating trace data. A traced program, or the operating system responsible for the traced program, writes index values to a particular hardware location, which index values become part of the trace data by operation of hardware devices in the target system. A debug-trace program (executed either in an attached host computer or as an embedded debugger) uses the index values to assist the user of the debug-trace program in navigating to particular portions of the trace data based on the index values.

Abstract: The trace interface and the trace receiver may be synchronized by the trace receiver controlling the pace of trace generation. The interface generates a clock signal coincident with valid trace data, and the trace receiver acknowledges the data by a change in state of an acknowledge signal. This enables generation of the next trace data point.

Abstract: Input processing limitations may be solved by placing multiple units in series, with each unit recording some portion of the incoming data. This requires the generation of simultaneous actions across units operating in series, with both the data recording and user command execution happening at the same point in the trace data stream.

Abstract: Code will switch to secure code via an exception only. All PC and data trace will be turned off during secure code. This will occur regardless of trace being in standard trace mode or event profiling mode. Timing, if on, will switch to standby mode. On return from the secure code, the switches that were already on will switch back and turn on. The address reported in the end sync point will be the address 0x01. Since this is an illegal address, this information is sufficient to indicate an end sync point was caused in secure code.

Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.

Abstract: A series of instructions from executable code are implemented on a processor core which in turn outputs event data. A watermark counter inputs event data and counts the number of events that occur within a time period defined by a start and stop signal. The watermark counter outputs a count value, corresponding to the number of events counted in the time period, across a connection to a monitoring computer.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: An information carrier medium containing debugging software that, when executed by a processor, causes the processor to receive information from hardware in communication with the processor, the information indicative of one or more no-operation instructions (NO-OPs) in software code stored on the hardware. The software also causes the processor to selectively replace at least one of the NO-OPs with an event-generating instruction (EGI). When executed, the EGI causes a circuit logic to generate one or more events.

Abstract: The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented changing state when new information is generated. The trace logic, whose clock is free running, detects the change in state in the valid signal. It then processes the trace information presented to it, exporting this information to a trace recorder. When transmission of this information has created sufficient space to accept a new frame of trace information, the empty signal is generated. This causes the clock generation logic to issue another clock to the system logic.

Abstract: A system comprises a circuit configured to execute instructions and output event data corresponding to the execution of the instructions. The system also comprises a monitoring device coupled to the circuit. The monitoring device receives information about said event data. The event data comprises event data selected from a group consisting of memory events and external events.

Abstract: A trace receiver with multiple recording interfaces may be used to record the same input. The historical control point for starting and stopping trace recording is placed very near the front end. A new control point further from the font end allows the front end to continue operation while data is either presented to the memory interface for storage or discarded.

Abstract: When events are traced, the timing stream is used to associate events with instructions and indicate pipeline advances precluding the recording of stall cycles. Additional information is needed in the trace stream to identify an overlay whose execution of code is in a system where overlays or a memory management unit are used. In the case of PC trace, additional information is added when the memory system contents is changed. Information describing the configuration change is inserted into the export streams by placing this information in a message buffer. As long as a message word is available for output, it becomes the next export word as the output of message words is continuous.