Abstract: A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace information indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.

Abstract: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command.

Abstract: A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further comprises an interface adapter counting a number of inert scans in the command window, and the number of inert scans defines a particular command or data. An inert scan results in no data being moved into or out of the interface adapter.

Abstract: A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur.

Abstract: An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.

Abstract: A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at least one zero-bit scans.

Abstract: A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.

Abstract: In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals and the system clock signals have the same frequency, both clock signals can applied to the integrated circuit through a single terminal, whereby providing a terminal for the exchange of other signals with the integrated circuit. Using the same signals for test and system clocks allows selected components to be eliminated.

Abstract: In selected JTAG states, the data input and output terminals are not used for several clock cycles. By recognizing the appropriate selected JTAG states and providing circuits to permit the transfer of non-JTAG data during these selected states, a more efficient use of the terminals which provide an interface between the emulation unit and the JTAG interface logic can be achieved.

Abstract: In a JTAG procedure, the electrical coupling normally dedicated to the TMS information is eliminated. Instead, the TDI line signals are reformatted into control packets and data packets. The control packets include one field that provides the TMS information. The control packets result in either the SHIFT DR state or the SHIFT IR state. The remaining field(s) in a control packet indicates the number of data signals to be transmitted in the data packet that is transferred in the shift state. The control packet/data packet format can support directly addressing or indirect addressing mode.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor. That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: In-circuit-emulation of an integrated circuit includes a digital data processor capable of executing program instructions. A first debug event is detected during normal program execution. The causes the in-circuit-emulation to suspend program execution except for real time interrupts. A debug frame counter increments on each interrupt and decrements on each return from interrupt. If a debug event is detected during an interrupt service routine, that interrupt service routine is suspended and the count of the debug frame counter is stored. Execution of other interrupt service routines in response to corresponding interrupts is still permitted. The integrated circuit includes plural debug event detectors and the debug frame count is stored at the detector detecting a debug event during an interrupt service routine. This permits a determination of the order of interrupts triggering debug events by reading the stored debug frame count from each debug event detector.

Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfers the data from the emulator to the first device driver.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor . That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfer the data from the emulator to the first device driver.