Patents by Inventor Gen Murakami
Gen Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960162Abstract: Provided is an anti-glare film excellent in anti-glare properties and capable of suppressing reflected scattered light. The anti-glare film includes an anti-glare layer, the anti-glare film having an uneven surface, wherein for an amplitude spectrum of elevation of the uneven surface, when a sum of amplitudes corresponding to spatial frequencies of 0.005 ?m?1, 0.010 ?m?1, and 0.015 ?m?1 is defined as AM1 and an amplitude at a spatial frequency of 0.300 ?m?1 is defined as AM2, AM1 is 0.070 ?m or more and 0.400 ?m or less, AM2 is 0.0050 ?m or more, and AM2<AM1.Type: GrantFiled: July 11, 2023Date of Patent: April 16, 2024Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Mitsuhiro Kuzuhara, Yukimitsu Iwata, Jun Tsujimoto, Shigeki Murakami, Gen Furui
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Patent number: 7476913Abstract: A light emitting device has a cup portion with a bottom surface opening, and one electrode of a light emitting element is connected to the cup portion. The other electrode of the light emitting element is connected to a lead set up from an inner space to outside the cup portion using the opening of the cup portion. Each electrode and lead of the light emitting device can be electrically connected without bonding wires. This prevents shadows or light unevenness from reflecting the shape of the bonding wire, thereby enhancing light-emission efficiency. As an alternative to setting up the lead from inside to the outside of the cup portion, the lead existing outside the cup portion and the other electrode are electrically connected via the bonding wire through the cup portion's opening. Thus, light outputted outside of the light emitting device is not intercepted by the bonding wire.Type: GrantFiled: August 10, 2004Date of Patent: January 13, 2009Assignees: Renesas Technology Corp., Hitachi Cable Precision Co., Ltd., Hitachi Cable, Ltd.Inventors: Hiroyuki Isobe, Gen Murakami, Toshikatsu Hiroe
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Publication number: 20080128724Abstract: A light emitting device in which the bottom surface of a cup portion is configured to have an opening, and one electrode of a light emitting element is electrically connected to the cup portion, and the other electrode of the light emitting element is electrically connected to a lead which is set up through an inner space from outside the cup portion by making use of the opening of the cup portion. As a result of this configuration, each electrode and each lead of the light emitting device can be electrically connected to each other without using a bonding wire. This makes it possible to prevent occurrence of a shadow or light unevenness reflecting shape of the bonding wire, thereby allowing an enhancement in light-emission efficiency.Type: ApplicationFiled: August 10, 2004Publication date: June 5, 2008Inventors: Hiroyuki Isobe, Gen Murakami, Toshikatsu Hiroe
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Patent number: 7317181Abstract: A surface mount type light-emitting unit includes a light-emitting device. A first lead is connected electrically to a first electrode of the light-emitting device. A second lead is connected electrically to a second electrodc of the light-emitting device. A clear insulator seals the light-emitting device, a section connecting the first electrode to the first lead and a section connecting the second electrode to the second lead. An end of the first lead, forming a reflecting section, is molded into a cup-shaped portion having a flat bottom. The light-emitting device is bonded to the flat bottom. A surface of the reflecting section opposed to the flat bottom is exposed to a surface of thc insulator.Type: GrantFiled: August 22, 2005Date of Patent: January 8, 2008Assignees: Hitachi Cable, Ltd., Stanley Electric Co. Ltd.Inventors: Gen Murakami, Tetsuya Saito, Atsushi Otaka, Toshiaki Morikawa, Tomoaki Abe, Dai Aoki
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Publication number: 20060054912Abstract: A surface mount type light-emitting unit composed of a light-emitting device, a first lead connected electrically with a first electrode of the light-emitting device, a second lead connected electrically with a second electrode of the light-emitting device, and a clear insulator for sealing the light-emitting device, a connecting section of the first electrode of the light-emitting device and the first lead, and a connecting section of the second electrode of the light-emitting device and the second lead wherein connecting terminal sections of the first and second leads for connecting them with external devices, respectively, are placed on a surface of the insulator, comprises an end of the first lead being molded into a cup-shaped portion having a flat bottom; the light-emitting device being bonded to the bottom inside a reflecting section corresponding to the molded cup-shaped portion of the first lead; and a surface opposed to that of the reflecting, section on which the light-emitting device has been bondType: ApplicationFiled: August 22, 2005Publication date: March 16, 2006Inventors: Gen Murakami, Tetsuya Saito, Atsushi Otaka, Toshiaki Morikawa, Tomoaki Abe, Dai Aoki
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Patent number: 6995510Abstract: A surface mount type light-emitting unit composed of a light-emitting device, a first lead connected electrically with a first electrode of the light-emitting device, a second lead connected electrically with a second electrode of the light-emitting device, and a clear insulator for sealing the light-emitting device, a connecting section of the first electrode of the light-emitting device and the first lead, and a connecting section of the second electrode of the light-emitting device and the second lead wherein connecting terminal sections of the first and second leads for connecting them with external devices, respectively, are placed on a surface of the insulator, comprises an end of the first lead being molded into a cup-shaped portion having a flat bottom; the light-emitting device being bonded to the bottom inside a reflecting section corresponding to the molded cup-shaped portion of the first lead; and a surface opposed to that of the reflecting section on which the light-emitting device has been bondeType: GrantFiled: June 25, 2002Date of Patent: February 7, 2006Assignees: Hitachi Cable, Ltd., Stanley Electric Co., Ltd.Inventors: Gen Murakami, Tetsuya Saito, Atsushi Otaka, Toshiaki Morikawa, Tomoaki Abe, Dai Aoki
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Patent number: 6981585Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.Type: GrantFiled: July 30, 2002Date of Patent: January 3, 2006Assignee: Renesas Technology Corp.Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 6919622Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: February 10, 2004Date of Patent: July 19, 2005Assignee: Renesas Technology Corp.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 6855893Abstract: A wiring board includes a predetermined wiring section disposed on an insulation board, and an electromagnetic shielding film is placed at a position close to the wiring section. A semiconductor device includes an electromagnetic shielding film disposed on a surface, on which an integrated circuit of a semiconductor chip has been formed, through an insulative film, a lead is provided on the electromagnetic shielding film through an insulative film, the lead is electrically connected to an external terminal of the semiconductor chip, and the resulting structured material is sealed with a sealing material; and a circuit board for electronic parts composed of a circuit board prepared by forming a plurality of leads on an insulating material, and a conductor disposed on the plurality of leads through an insulating material and reducing a self inductance of the plurality of leads by flowing an eddy current through the conductor.Type: GrantFiled: November 27, 2002Date of Patent: February 15, 2005Assignee: Hitachi Cable Ltd.Inventors: Toyohiko Kumakura, Gen Murakami, Tomo Yasuda, Masahiko Kobayashi, Hidetoshi Murakami
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Publication number: 20040211591Abstract: There are provided a wiring board, wherein a predetermined wiring section is disposed on an insulation board, and an electromagnetic shielding film is placed at a position close to the wiring section; a semiconductor device, wherein an electromagnetic shielding film is disposed on a surface, on which an integrated circuit of a semiconductor chip has been formed, through an insulative film, a lead is provided on the electromagnetic shielding film through an insulative film, the lead is electrically connected to an external terminal of the semiconductor chip, and the resulting structured material is sealed with a sealing material; and a circuit board for electronic parts composed of a circuit board prepared by forming a plurality of leads on an insulating material, and a conductor disposed on the plurality of leads through an insulating material and reducing a self inductance of the plurality of leads by flowing an eddy current through the conductor.Type: ApplicationFiled: November 27, 2002Publication date: October 28, 2004Applicant: HITACHI CABLE LTD.Inventors: Toyohiko Kumakura, Gen Murakami, Tomo Yasuda, Masahiko Kobayashi, Hidetoshi Murakami
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Publication number: 20040155323Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: ApplicationFiled: February 10, 2004Publication date: August 12, 2004Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 6720208Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: December 19, 2002Date of Patent: April 13, 2004Assignee: Renesas Technology CorporationInventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Publication number: 20030127712Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: ApplicationFiled: December 19, 2002Publication date: July 10, 2003Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Publication number: 20030107316Abstract: A surface mount type light-emitting unit composed of a light-emitting device, a first lead connected electrically with a first electrode of the light-emitting device, a second lead connected electrically with a second electrode of the light-emitting device, and a clear insulator for sealing the light-emitting device, a connecting section of the first electrode of the light-emitting device and the first lead, and a connecting section of the second electrode of the light-emitting device and the second lead wherein connecting terminal sections of the first and second leads for connecting them with external devices, respectively, are placed on a surface of the insulator, comprises an end of the first lead being molded into a cup-shaped portion having a flat bottom; the light-emitting device being bonded to the bottom inside a reflecting section corresponding to the molded cup-shaped portion of the first lead; and a surface opposed to that of the reflecting section on which the light-emitting device has been bondeType: ApplicationFiled: June 25, 2002Publication date: June 12, 2003Inventors: Gen Murakami, Tetsuya Saito, Atsushi Otaka, Toshiaki Morikawa, Tomoaki Abe, Dai Aoki
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Publication number: 20030057113Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.Type: ApplicationFiled: July 30, 2002Publication date: March 27, 2003Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 6531760Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: April 25, 2000Date of Patent: March 11, 2003Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Publication number: 20020179460Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.Type: ApplicationFiled: July 30, 2002Publication date: December 5, 2002Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Publication number: 20020174627Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.Type: ApplicationFiled: July 30, 2002Publication date: November 28, 2002Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 6443298Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device. A caution is provided for the bag, that the devices should be presented from moisture absorption after opening the bag.Type: GrantFiled: April 30, 2001Date of Patent: September 3, 2002Assignee: Hitachi, Ltd.Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 6433409Abstract: A semiconductor device, comprising: a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion; an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and a molding resin for sealing said joined portion including the solder, wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin, the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa, and the solder compriType: GrantFiled: January 8, 2001Date of Patent: August 13, 2002Assignee: Hitachi Cable Ltd.Inventors: Mamoru Mita, Gen Murakami