Patents by Inventor Gen Murakami
Gen Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5514905Abstract: A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.Type: GrantFiled: October 27, 1994Date of Patent: May 7, 1996Assignee: Hitachi, Ltd.Inventors: Toshiyuki Sakuta, Kazuyuki Miyazawa, Satoshi Oguchi, Aizo Kaneda, Masao Mitani, Shozo Nakamura, Kunihiko Nishi, Gen Murakami
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Patent number: 5448105Abstract: A leadframe according to this invention is formed by bonding a single leadframe with a substrate using adhesive film or double-sided adhesive resin film, which is divided and attached to two or more predetermined points between them. This reduces the quantity of gas or contaminants generated from adhesives. Also, this results in the reduction of the stress generated during heat treatment of the leadframe and also in the elimination of warping of the lead frame due to thermal stress. Cracking does not occur on the resin because resin is removed easily and assuredly, and no air is left behind. This contributes to high reliability and increased productivity. The lead frame is further formed by bonding a plurality of metal substrates of different materials to single leadframe. This through more stable thermal behavior high reliability.Type: GrantFiled: January 17, 1995Date of Patent: September 5, 1995Assignees: Dia Nippon Printing Co., Ltd., Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazunori Katoh, Gen Murakami, Hiromichi Suzuki, Takayuki Okinaga, Takashi Emata, Osamu Horiuchi
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Patent number: 5442233Abstract: A lead frame for a semiconductor IC device has a pair of common elongated leads and first and second groups of slender leads arranged on opposite sides of the common elongated leads and generally extending transverse to the common elongated leads. The common elongated leads have as their integral parts slender leads extending therefrom generally transverse thereto and substantially linear extensions from both ends of the common elongated leads. The linear extensions serve to firmly support a semiconductor chip to be packaged along with parts of the leads. The common elongated leads may further have as their integral parts projections extending from their sides for enhancement of the heat dissipation capability. A semiconductor chip may have bonding pads arranged thereon such that bonding wires and the common elongated leads do not cross each other for electrical connection between the common elongated leads and bonding pads of the semiconductor chip.Type: GrantFiled: December 10, 1992Date of Patent: August 15, 1995Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Ichiro Anjoh, Gen Murakami, Michael A. Lamson, Katherine G. Heinen
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Patent number: 5365113Abstract: A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.Type: GrantFiled: January 4, 1993Date of Patent: November 15, 1994Assignee: Hitachi, Ltd.Inventors: Toshiyuki Sakuta, Kazuyuki Miyazawa, Satoshi Oguchi, Aizo Kaneda, Masao Mitani, Shozo Nakamura, Kunihiko Nishi, Gen Murakami
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Patent number: 5358904Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: December 14, 1992Date of Patent: October 25, 1994Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
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Patent number: 5357139Abstract: In a package for DRAM, plastic is included between the common signal inner leads (bus bar inner leads) and insulating films arranged in the central part of a semiconductor chip. Thus, the deformation of plastic at the upper edge of the common signal inner leads is reduced and no great stress is generated at this portion. Accordingly, plastic cracking can be prevented.Type: GrantFiled: September 8, 1993Date of Patent: October 18, 1994Assignee: Hitachi, Ltd.Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
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Patent number: 5332922Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.Type: GrantFiled: April 26, 1991Date of Patent: July 26, 1994Assignee: Hitachi, Ltd.Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Miyamoto, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe
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Patent number: 5304844Abstract: A semiconductor device is provided having a semiconductor pellet that is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base. External terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, as well as inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.Type: GrantFiled: May 28, 1992Date of Patent: April 19, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Osamu Horiuchi, Gen Murakami, Hiromichi Suzuki, Hajime Hasebe, Kanji Otsuka, Yuuji Shirai, Takayuki Okinaga, Takashi Emata
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Patent number: 5295297Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.Type: GrantFiled: July 20, 1992Date of Patent: March 22, 1994Assignee: Hitachi, Ltd.Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 5296737Abstract: A semiconductor device comprises a plurality of semiconductor chips; electrodes formed on circuit surfaces of said plurality of semiconductor chips; inner leads made of a metal foil and bonded at first ends thereof to the electrodes, outer leads each having a predetermined surface at a first end thereof bonded to a second end of at least one of the inner leads, and a sealing material sealing said plurality of semiconductor chips, the electrodes, the inner leads, and part of each of the outer leads. The semiconductor chips are laminated in such a manner that those surfaces of the semiconductor chips on which their respective circuits are formed are disposed in facing relation to each other. This provides a semiconductor device which is excellent in assembling efficiency.Type: GrantFiled: September 6, 1991Date of Patent: March 22, 1994Assignee: Hitachi, Ltd.Inventors: Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Gen Murakami, Ichiro Anjoh
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Patent number: 5274914Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.Type: GrantFiled: July 20, 1992Date of Patent: January 4, 1994Assignee: Hitachi, Ltd.Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 5256903Abstract: A plastic encapsulated semiconductor device containing one or more of insulating films. Uneven surfaces, such as recesses and roughened surfaces, are strategically provided on peripheral side (edge) surfaces of the insulating films. As a result, therefore, an interface separation does not easily occur between the side surfaces of the insulating films and the encapsulating resin. If such an interface separation should occur, it cannot develop easily. Thus, it is possible to obtain a plastic encapsulated semiconductor device of a high level of reliability even when the largest possible semiconductor element is mounted therein within limited outside dimensions.Type: GrantFiled: November 26, 1991Date of Patent: October 26, 1993Assignee: Hitachi Ltd.Inventors: Maya Obata, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
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Patent number: 5235207Abstract: A semiconductor device having a semiconductor chip that has a square main surface in which a plurality of elements are formed on the main surface of the chip, and in which first and second bonding pads are arranged along the periphery of the main surface. A plurality of first leads are provided in which the first and second ends thereof are positioned outside of the semiconductor chip. A second lead is also provided that extends on the main surface of the semiconductor chip and extends to the outside of the semiconductor chip. The device is additionally provided with electrical connections between the first bonding pads and the first ends of the first leads, second electrical connections between the second bonding pads and the second lead and a sealing material that covers the semiconductor chip, the first leads, a portion of the second lead, and the first and second electrical connections.Type: GrantFiled: December 2, 1992Date of Patent: August 10, 1993Assignee: Hitachi, Ltd.Inventors: Eiji Ohi, Hiromichi Suzuki, Gen Murakami
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Patent number: 5194935Abstract: The plastic encapsulated semiconductor device according to the present invention has a semiconductor chip, leads, and members for electrically connecting these parts to each other. A part of leads, the semiconductor chip and the connecting members are encapsulated with a plastic to form a package. The plate type plastic fins formed on the surface of and integrally with the package are divided in two directions perpendicular to each other thereby forming, for example, rows and columns of fins or fin segments, on the package surface. Therefore, the semiconductor device according to the present invention can be molded easily by a transfer molding. It has a high reliability with respect to the prevention of cracks in the plastic, and a low thermal resistance, and is most suitably used to obtain a high-density package mounting structure.Type: GrantFiled: January 29, 1991Date of Patent: March 16, 1993Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Sueo Kawai, Gen Murakami, Ichio Shimizu
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Patent number: 5184208Abstract: A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.Type: GrantFiled: January 14, 1991Date of Patent: February 2, 1993Assignee: Hitachi, Ltd.Inventors: Toshiyuki Sakuta, Kazuyuki Miyazawa, Satoshi Oguchi, Aizo Kaneda, Masao Mitani, Shozo Nakamura, Kunihiko Nishi, Gen Murakami
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Patent number: 5150193Abstract: The present invention consists in that a through hole of large area is provided in a die pad or a tab, thereby to prevent a resin from cracking at the rear surface of a surface-packaging resin package in a high-temperature soldering atmosphere of vapor-phase reflow or the like, whereby a resin-molded surface-packaged IC of high reliability is provided.Type: GrantFiled: February 11, 1991Date of Patent: September 22, 1992Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.Inventors: Toshihiro Yasuhara, Masachika Masuda, Gen Murakami, Kunihiko Nishi, Masanori Sakimoto, Ichio Shimizu, Akio Hoshi, Sumio Okada, Tooru Nagamine
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Patent number: 5095626Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices wherein the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.Type: GrantFiled: August 10, 1989Date of Patent: March 17, 1992Assignee: Hitachi, Ltd.Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Patent number: 5068712Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: September 19, 1989Date of Patent: November 26, 1991Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 5032895Abstract: A semiconductor device comprising the fact that a semiconductor pellet is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base, and that external terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, and inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.Type: GrantFiled: April 18, 1990Date of Patent: July 16, 1991Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Osamu Horiuchi, Gen Murakami, Hiromichi Suzuki, Hajime Hasebe, Kanji Otsuka, Yuuji Shirai, Takayuki Okinaga, Takashi Emata
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Patent number: 4994411Abstract: A process of producing a semiconductor device involving the steps of providing a lead frame having inner leads spaced from each other and connected together by a connecting portion; bonding a layer of an insulating material to the connecting portion and to surrounding portions of the inner leads; removing the connecting portion and a portion of the layer of insulating material to form end portions of the inner leads which are separated from each other and retained in a spaced arrangement by a remaning portion of the layer of insulating material; joining a semiconductor chip having bonding pads to the end portions of the inner leads; connecting the bonding pads on the semiconductor chip and the inner leads by wires; and encapsulating the semiconductor chip, the remaining portion of the layer of insulating material, the inner leads and the wires within a resin material; a peripheral portion of one face of the semiconductor chip partially overlapping faces of the end portions.Type: GrantFiled: March 10, 1989Date of Patent: February 19, 1991Assignee: Hitachi, Ltd.Inventors: Takahiro Naito, Gen Murakami, Hiromichi Suzuki, Hajime Sato, Wahei Kitamura, Masachika Masuda