Abstract: In order to provide a home user with cost-effective PC processing capability, the home user is provided with a terminal which has only sufficient processing capability to communicate with a service provider over a network. Any processing and program execution is performed, in response to requests from the home user's terminal, by the service provider and the results are returned to the terminal. In addition to the processing capability, data is stored in the service provider. Because the processing and data storage is performed by the service provider, changes to the programs and/or hardware can the confined to the processing resources of the service provider. In addition, the service provider can be provided with virus and hacking protection, protection that will then not be necessary for the home user's terminal.

Abstract: An input/output device has a light source in optical communication with a digital mirror device (DMD) special light modulator for projecting an image and an image sensor in optical communication along a shared optical path with the same spatial light modulator for receiving an image.

Abstract: In an optical image acquisition and information transmission system, the system components can be fabricated, according to a first implementation, in a stack positioned on a circuit board. According to a second implementation, the system components are fabricated on a single substrate using the same semiconductor processes for each component. Both implementations result in better performance parameters. These systems are particularly useful as control devices wherein information resulting from processing the acquired image rather than the image itself is transmitted.

Abstract: Embodiments of the invention to provide methods to provide on demand product placement to web based content. A method of in accordance with an embodiment of includes obtaining agreement between entities for placing a product in content. The products image or region of interest in the content is manipulated such that the product is emphasized; and content provider obtains payment for the content based activity of the content.

Abstract: A recording and playback system comprising a personal video recorder (“PVR”) coupled to a television monitor. The PVR records a video broadcast stream which comprises main program information as well as commercial content. The commercial content includes commercial identifier values which indicate to the PVR the presence of commercial content. Thus, during playback on the monitor, the PVR monitors the recorded broadcast stream for the commercial identifiers to determine the presence of commercial content. A user can control the PVR to play back the recorded stream in a conventional manner in which commercials interrupt the main program information. Alternatively, the user can cause the PVR to play back the recorded broadcast stream in an alternate format in which the main program information continues to play concurrently with the commercial content.

Abstract: A media player coupled to a network contains a processor, non-volatile memory, volatile memory, a driver, and input and output ports. The media player receives a media file over the network that contains an encoded media stream and a universal decoder. The player's processor converts or translates (or otherwise generates) the universal decoder into a player-specific decoder which may differ from the universal decoder. A library of routines stored in the non-volatile memory is used to create the player-specific decoder. The media stream downloaded to the media player may comprise audio, video, or any other desired type of media. In this manner, each media player can generate a decoder that differs, not only from the universal decoder, but may also differ from other media players thereby alleviating the burden on the media source from having to download the encoded media with a decoder specific to the target media player.

Abstract: In an optical image acquisition and information transmission system, the system components can be fabricated, according to a first implementation, in a stack positioned on a circuit board. According to a second implementation, the system components are fabricated on a single substrate using the same semiconductor processes for each component. Both implementations result in better performance parameters. These systems are particularly useful as control devices wherein information resulting from processing the acquired image rather than the image itself is transmitted.

Abstract: In order to provide a home user with cost-effective PC processing capability, the home user is provided with a terminal which has only sufficient processing capability to communicate with a service provider over a network. Any processing and program execution is performed, in response to requests from the home user's terminal, by the service provider and the results are returned to the terminal. In addition to the processing capability, data is stored in the service provider. Because the processing and data storage is performed by the service provider, changes to the programs and/or hardware can the confined to the processing resources of the service provider. In addition, the service provider can be provided with virus and hacking protection, protection that will then not be necessary for the home user's terminal.

Abstract: In order to prevent unauthorized usage of a software program, the software program is encrypted using at least a part of a serial number or other identifying number stored in the processing unit as the encryption key. The software program is stored in encrypted form in the processing unit memory. When the processing unit requires the use of the software program, the program is encrypted using the internally stored serial or identifying number.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: The user receives a digital radio transmission through a digital receiver and transmits a request to download selected content from this transmission to a content agent, an entity responsible for authorizing the authorized downloading of the digital content. If the content is not free of charge, the user also transmits sufficient information to allow for payment for the digital. The user then receives a transmission authorizing the downloading of the digital content from the content agent upon acceptance of the payment by the content agent. The user then downloads the content to a storage device which is coupled to the receiver.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).