Patents by Inventor Gene Frantz
Gene Frantz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6732225Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 2, 2003Date of Patent: May 4, 2004Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6728828Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: May 23, 2003Date of Patent: April 27, 2004Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6728829Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: May 30, 2003Date of Patent: April 27, 2004Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6662291Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: July 5, 2002Date of Patent: December 9, 2003Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030208669Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 30, 2003Publication date: November 6, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030200417Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030200415Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 23, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030200416Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 30, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030200381Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 30, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196067Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196068Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196070Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196034Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 30, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196069Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030037219Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asychronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: July 5, 2002Publication date: February 20, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030033449Abstract: A media player coupled to a network contains a processor, non-volatile memory, volatile memory, a driver, and input and output ports. The media player receives a media file over the network that contains an encoded media stream and a universal decoder. The player's processor converts or translates (or otherwise generates) the universal decoder into a player-specific decoder which may differ from the universal decoder. A library of routines stored in the non-volatile memory is used to create the player-specific decoder. The media stream downloaded to the media player may comprise audio, video, or any other desired type of media. In this manner, each media player can generate a decoder that differs, not only from the universal decoder, but may also differ from other media players thereby alleviating the burden on the media source from having to download the encoded media with a decoder specific to the target media player.Type: ApplicationFiled: July 17, 2002Publication date: February 13, 2003Inventors: Gene A. Frantz, Pedro Gelabert, Mark Nadeski, Jason Kridner
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Publication number: 20020176702Abstract: A recording and playback system comprising a personal video recorder (“PVR”) coupled to a television monitor. The PVR records a video broadcast stream which comprises main program information as well as commercial content. The commercial content includes commercial identifier values which indicate to the PVR the presence of commercial content. Thus, during playback on the monitor, the PVR monitors the recorded broadcast stream for the commercial identifiers to determine the presence of commercial content. A user can control the PVR to play back the recorded stream in a conventional manner in which commercials interrupt the main program information. Alternatively, the user can cause the PVR to play back the recorded broadcast stream in an alternate format in which the main program information continues to play concurrently with the commercial content.Type: ApplicationFiled: May 8, 2002Publication date: November 28, 2002Inventor: Gene A. Frantz
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Patent number: 6418078Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: December 21, 2000Date of Patent: July 9, 2002Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20010000817Type: ApplicationFiled: December 21, 2000Publication date: May 3, 2001Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6188635Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: February 13, 2001Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait