Patents by Inventor Geng Wang

Geng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403772
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Juntao Li, Kangguo Cheng, Chengwen Pei, Geng Wang, Joseph Ervin
  • Patent number: 10396169
    Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10375937
    Abstract: The present invention discloses a breeding method for obtaining heterosis in lined seahorses, which comprises the following steps: S1, selecting parents of lined seahorse from populations with great differences in genetic background; S2, intensified rearing the parents before pregnancy; S3, matching and breeding the parents of lined seahorse from different geographical populations according to complete diallel cross method; S4, finely nursing pregnant seahorses; S5, respectively collecting all postlarvae (filial generations) hatched by each breeding group in one week; S6, rearing the filial generations; and S7, comparing survival rate and growth performance of filial generations. The present invention, via hybridization of different geographical populations to obtain lined seahorse, makes effective use of heterosis. Survival rate and growth rate of filial generations are apparently enhanced compared to that of those filial generations without hybridization.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 13, 2019
    Assignee: SOUTH CHINA SEA INSTITUTE OF OCEANOLOGY
    Inventors: Wei Luo, Qiang Lin, Geng Qin, Xin Wang, Yanhong Zhang, Huixian Zhang
  • Publication number: 20190220640
    Abstract: A method for detecting a two-dimensional barcode is provided. Binarization processing is performed on an image to obtain a binary image. Whether the binary image has a target pattern is determined, and it is determined that the binary image has a two-dimensional barcode in response to determining that the binary image has the target pattern. An enlarged image of the two-dimensional barcode is obtained, and two-dimensional barcode detection is performed on the enlarged image of the two-dimensional barcode.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Dian Ping XU, Yu Geng LIN, Chen RAN, Hong Yang WANG, Zhang Jing YANG, Jun Jie ZHOU, Pin Lin CHEN, Jing WU, Han Qi ZHANG
  • Publication number: 20190206341
    Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a plurality of sub-pixels arranged in matrix, each sub-pixels is an eight domains structure; in a frame image, the data signals of the sub-pixels in two adjacent columns have opposite polarities, and in two adjacent frame images, the data signals of the same sub-pixel have opposite polarities; each two adjacent sub-pixels in a row direction are a sub-pixel group, in two adjacent sub-pixel groups, the sub-pixels in one sub-pixel group display a brightness of a first display gray scale corresponding to the sub-pixels, the sub-pixels in another sub-pixel group display a brightness of a second display gray scale corresponding to the sub-pixels; by performing the color shift compensation process on the data signals of the sub-pixels in the eight-domain structure, the color viewing angle and the viewing experience of the liquid crystal display device could be improved.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 4, 2019
    Inventors: Bingjei LIAO, Yu WU, Xiaoliang GUAN, Geng WANG
  • Patent number: 10330771
    Abstract: Neighbor cell hearability can be improved by including an additional reference signal that can be detected at a low sensitivity and a low signal-to-noise ratio, by introducing non-unity frequency reuse for the signals used for a time difference of arrival (TDOA) measurement, e.g., orthogonality of signals transmitted from the serving cell sites and the various neighbor cell sites. The new reference signal, called the TDOA-RS, is proposed to improve the hearability of neighbor cells in a cellular network that deploys 3GPP EUTRAN (LTE) system, and the TDOA-RS can be transmitted in any resource blocks (RB) for PDSCH and/or MBSFN subframe, regardless of whether the latter is on a carrier supporting both PMCH and PDSCH or not. Besides the additional TDOA-RS reference signal, an additional synchronization signal (TDOA-sync) may also be included to improve the hearability of neighbor cells.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: Lai King Tee, Geng Wu, Jun Li, Yuqiang Tang, Neng Wang, Hua Xu, Jianglei Ma
  • Publication number: 20190189625
    Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10324709
    Abstract: The present invention relates to an apparatus and a method for validating application deployment topology in a cloud environment. There is provided an apparatus for validating application deployment topology in a cloud environment comprising: a topology skeleton generator configured to generate, based on multiple VMs and script packages running on the VMs created by a user and required to deploy an application as well as running order of script packages and data dependency between script packages set by the user, a topology skeleton that comprises at least scripts of script packages of respective VMs and running order of the script packages; and a simulator configured to simulate a runtime environment in the cloud environment at the apparatus, thereby validating the running order and data dependency with respect to the topology skeleton, wherein the simulator is installed in the apparatus by using a simulator installation package retrieved from the cloud environment.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Geng Du, Chong Feng, Wei Feng Li, Xin Li, Qi Liu, Qiang Wang, Yue Wang, Chunxiao Zhang
  • Patent number: 10290574
    Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Geng Wang, Kangguo Cheng, Chengwen Pei, Juntao Li
  • Publication number: 20190123056
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10269790
    Abstract: A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10249539
    Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10249709
    Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10243054
    Abstract: Embodiments of the invention are directed to fabrication operations for co-integrating standard-gate (SG) and extended-gate (EG) nanosheet/nanowire transistors on the same substrate. The SG and EG nanosheet/nanowire transistors share certain fabrication operations for certain features. For example, the processes to form the bottommost channel nanosheet, the bottommost sacrificial nanosheet, and the topmost channel nanosheet are the same for SG nanosheet transistors and the EG nanosheet transistors. Because the thickness of the sacrificial nanosheet needs to be thicker for EG nanosheet transistors, a thickness of the bottommost sacrificial nanosheet is selected to accommodate the design parameters of the EG nanosheet transistor. Because the thickness of the SG and the EG channel nanosheets do not need to be different, a thickness of the bottommost channel nanosheet and the topmost channel nanosheet can be selected to accommodate the design parameters of both the SG and the EG nanosheet transistors.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10236382
    Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10236381
    Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10229920
    Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Qintao Zhang, Juntao Li, Geng Wang
  • Patent number: 10229919
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10224329
    Abstract: Methods of forming semiconductor devices include forming structures having an inner vertical layer and spacers on sidewalls of the inner vertical layer on a first region and a second region of a gate layer. The inner vertical layer is etched in only the first region to expose inner sidewalls of the spacers in the first region. The gate layer is etched using the remaining inner vertical layers and the spacers as a mask to form first gates in the first region and second gates in the second region. The first gates have a smaller gate length than a gate length of the second gates.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10224334
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang