Abstract: A semiconductor device having transistors and anti-fuses integrated thereon includes a transistor region having a defect free monocrystalline semiconductor layer and a device channel for a transistor. The device also has an anti-fuse region including a defective semiconductor layer formed on an oxide of a portion of the surface of an epitaxial semiconductor layer over which the transistor is formed, the oxide having a thickness extending into the epitaxial semiconductor layer. It also has gate structures formed in the transistor region and in the anti-fuse region, where the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: A driving method of a display panel and a display device are provided. The method includes: receiving an external display data; changing a luminance signal of the sub-pixel corresponding to each pixel unit of a display panel in the display data, to generate a data signal; sending the data signal; wherein the luminance of one sub-pixel in the two adjacent sub-pixels in the same color after being changed, is greater than the luminance before being changed, and the luminance of the other sub-pixel after being changed, is smaller than the luminance before being changed. The present disclosure can make the orientation of the liquid crystal molecules in the liquid crystal display panel may be more rich, and the chromaticity viewing angle of the liquid crystal display panel may be improved.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a plurality of sub-pixels arranged in matrix, each sub-pixels is an eight domains structure; in a frame image, the data signals of the sub-pixels in two adjacent columns have opposite polarities, and in two adjacent frame images, the data signals of the same sub-pixel have opposite polarities; each two adjacent sub-pixels in a row direction are a sub-pixel group, in two adjacent sub-pixel groups, the sub-pixels in one sub-pixel group display a brightness of a first display gray scale corresponding to the sub-pixels, the sub-pixels in another sub-pixel group display a brightness of a second display gray scale corresponding to the sub-pixels; by performing the color shift compensation process on the data signals of the sub-pixels in the eight-domain structure, the color viewing angle and the viewing experience of the liquid crystal display device could be improved.

Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.

Abstract: A semiconductor device having transistors and anti-fuses integrated thereon includes a transistor region having a defect free monocrystalline semiconductor layer and a device channel for a transistor. The device also has an anti-fuse region including a defective semiconductor layer formed on an oxide of a portion of the surface of an epitaxial semiconductor layer over which the transistor is formed, the oxide having a thickness extending into the epitaxial semiconductor layer. It also has gate structures formed in the transistor region and in the anti-fuse region, where the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.

Abstract: A driving method of a display panel and a display device are provided. The method includes: receiving an external display data; changing a luminance signal of the sub-pixel corresponding to each pixel unit of a display panel in the display data, to generate a data signal; sending the data signal; wherein the luminance of one sub-pixel in the two adjacent sub-pixels in the same color after being changed, is greater than the luminance before being changed, and the luminance of the other sub-pixel after being changed, is smaller than the luminance before being changed. The present disclosure can make the orientation of the liquid crystal molecules in the liquid crystal display panel may be more rich, and the chromaticity viewing angle of the liquid crystal display panel may be improved.

Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

Abstract: A method of making an inductor device includes forming a first metal layer and an ILD on a substrate, patterning a trench perpendicular to the first metal layer in the ILD, and depositing a magnetic material. The method includes depositing another ILD and patterning a via adjacent to the trench that extends from the first metal layer to a surface of the ILD. The method includes patterning trenches in the ILD, with a first portion over and adjacent to and parallel to the first metal layer, and a second portion perpendicular to the first portion and extending from an end of the first portion to the via. The first metal layer and trenches are connected to through the via. The method includes depositing a metal in the via, and depositing a metal in the trenches to form a second metal layer connected to the first metal layer through the via.

Abstract: Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a plurality of sub-pixels arranged in matrix, each sub-pixels is an eight domains structure; in a frame image, the data signals of the sub-pixels in two adjacent columns have opposite polarities, and in two adjacent frame images, the data signals of the same sub-pixel have opposite polarities; each two adjacent sub-pixels in a row direction are a sub-pixel group, in two adjacent sub-pixel groups, the sub-pixels in one sub-pixel group display a brightness of a first display gray scale corresponding to the sub-pixels, the sub-pixels in another sub-pixel group display a brightness of a second display gray scale corresponding to the sub-pixels; by performing the color shift compensation process on the data signals of the sub-pixels in the eight-domain structure, the color viewing angle and the viewing experience of the liquid crystal display device could be improved.

Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.