Patents by Inventor Geng Wang

Geng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180061844
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Publication number: 20180053767
    Abstract: Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Publication number: 20180053758
    Abstract: An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.
    Type: Application
    Filed: September 7, 2017
    Publication date: February 22, 2018
    Inventors: KANGGUO CHENG, JUNTAO LI, GENG WANG, QINTAO ZHANG
  • Patent number: 9899383
    Abstract: A chip includes multiple first transistors in a first region and multiple second transistors in a second region. A gap between adjacent first transistors has a same width as a gap between adjacent second transistors. Gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 9898177
    Abstract: A display processing method that is applied in a portable mobile terminal, to display multiple objects on a touch screen of the portable mobile terminal. The method includes obtaining a touch point that is a point created when an operating object contacts/almost touches the touch screen; determining a preset area with the touch point being the center; determining a first object and a second object, among multiple objects, each intersecting with the preset area on at least one point; determining a first information of the movement of the first object, the first information indicating moving the first object from a first position to a second position, the first position being the original position of the first object displayed on the touch screen; and moving the first object from the first position to the second position according to the first information.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 20, 2018
    Assignees: BEIJING LENOVO SOFTWARE LTD., LENOVO (BEIJING) CO., LTD.
    Inventors: Geng Wang, Ran Sun
  • Patent number: 9899391
    Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 9881998
    Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Publication number: 20180012897
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Application
    Filed: September 1, 2017
    Publication date: January 11, 2018
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 9859373
    Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
  • Publication number: 20170373005
    Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 28, 2017
    Inventors: Chengwen Pei, Kangguo Cheng, Juntao Li, Geng Wang
  • Publication number: 20170373148
    Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 28, 2017
    Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 9852982
    Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengwen Pei, Kangguo Cheng, Juntao Li, Geng Wang
  • Publication number: 20170365713
    Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.
    Type: Application
    Filed: February 2, 2017
    Publication date: December 21, 2017
    Inventors: KANGGUO CHENG, JUNTAO LI, GENG WANG, QINTAO ZHANG
  • Publication number: 20170365725
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: Juntao LI, Kangguo CHENG, Chengwen PEI, Geng WANG, Joseph ERVIN
  • Patent number: 9847246
    Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 9842835
    Abstract: Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor and diode regions. The method further includes depositing a mask, where the mask covers only the field-effect transistor region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the field-effect transistor region, and depositing a metal over the substrate to create terminals.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 9806084
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Publication number: 20170309626
    Abstract: A chip includes multiple first transistors in a first region and multiple second transistors in a second region. A gap between adjacent first transistors has a same width as a gap between adjacent second transistors. Gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.
    Type: Application
    Filed: March 23, 2017
    Publication date: October 26, 2017
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Publication number: 20170309622
    Abstract: Semiconductor devices and methods of forming the same include forming mandrels on a first region and a second region of a gate layer. First spacers are formed on sidewalls of the mandrels. The mandrels are etched away to expose inner sidewalls of the first spacers. Second spacers are formed on sidewalls of the first spacers. First spacers in only the first region are etched away to expose inner sidewalls of the second spacers in the first region. The gate layer is etched using the remaining first spacers and the second spacers as a mask to form first gates in the first region and second gates in the second region. The first gates have a gate length than the second gates.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 26, 2017
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: D805091
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 12, 2017
    Assignee: Neusoft Corporation
    Inventors: Qianhui Guo, Qizhen Pei, Xiangpeng Chen, Geng Wang, Hongliang Pang, Qian Zhang